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Adaptive computing systems (ACS) rely on reconfigurable hardware to adapt the system operation to changes in the external environment, and to extend mission capability by implementing new functions on the same hardware platform. This results in increased functional density and reduced power consumption - features very important in many domains, such as space missions or mobile devices. Field-programmable gate arrays (FPGAs) featuring incremental dynamic runtime reconfiguration (RTR) offer additional benefits by allowing the system to continue to execute uninterrupted, while portions of the FPGA are reconfigured for new logic functions. ACS are often deployed in harsh and/or hostile remote environments, and they are subject to strict high-reliability and high-availability requirements. Cosmic radiation may perturb the operation of a defect-free FPGA, and marginal defects not causing failures in manufacturing testing (such as a short initially having very high resistance) may become active with the aging of the device, or because of environmental factors. Since direct human intervention for maintenance and repair is impossible in such environments, fault-tolerant (FT) techniques resulting in graceful degradation must be used to achieve the desired mission life even in the presence of faults. However, traditional FT design, based on replicated modular redundancy and voting, is extremely expensive given the space, weight, and power constraints of ACS.

Adaptive computing systems (ACS) rely on reconfigurable hardware to adapt the system operation to changes in the external environment, and to extend mission capability by implementing new functions on the same hardware platform. This results in increased functional density and reduced power consumption - features very important in many domains, such as space missions or mobile devices. Field-programmable gate arrays (FPGAs) featuring incremental dynamic runtime reconfiguration (RTR) offer additional benefits by allowing the system to continue to execute uninterrupted, while portions of the FPGA are reconfigured for new logic functions. ACS are often deployed in harsh and/or hostile remote environments, and they are subject to strict high-reliability and high-availability requirements. Cosmic radiation may perturb the operation of a defect-free FPGA, and marginal defects not causing failures in manufacturing testing (such as a short initially having very high resistance) may become active with the aging of the device, or because of environmental factors. Since direct human intervention for maintenance and repair is impossible in such environments, fault-tolerant (FT) techniques resulting in graceful degradation must be used to achieve the desired mission life even in the presence of faults. However, traditional FT design, based on replicated modular redundancy and voting, is extremely expensive given the space, weight, and power constraints of ACS.

The aim of this work is to enable a more rigorously tested product by integrating protocol specification and conformance test sequence generation. Such an integration will allow for the removal of costly mistakes from a specification at an early stage of the development process before they propagate into different implementations, possibly combined with other errors. This integrated approach has been applied to the VHDL specification of a military-oriented protocol prototype called the "Local Proxy." Based on the results of the conformance test generation process, the Local Proxy specification has been refined by uncovering various missing actions, removing redundancies, and restructuring the specification to improve its testability.

This short paper describes early experiments to validate the capabilities of a component-based platform to observe and control a software architecture in the small. This is part of a whole process for resilient computing, i.e. targeting the adaptation of fault-tolerance mechanisms at runtime.

Massively parallel desktop computing capabilities now well within the reach of individual academics modify the environment for posterior simulation in fundamental and potentially quite advantageous ways. But to fully exploit these benefits algorithms that conform to parallel computing environments are needed. Sequential Monte Carlo comes very close to this ideal whereas other approaches like Markov chain Monte Carlo do not. This paper presents a sequential posterior simulator well suited to this computing environment. The simulator makes fewer analytical and programming demands on investigators, and is faster, more reliable and more complete than conventional posterior simulators. The paper extends existing sequential Monte Carlo methods and theory to provide a thorough and practical foundation for sequential posterior simulation that is well suited to massively parallel computing environments. It provides detailed recommendations on implementation, yielding an algorithm that requires only code for simulation from the prior and evaluation of prior and data densities and works well in a variety of applications representative of serious empirical work in economics and finance. The algorithm is robust to pathological posterior distributions, generates accurate marginal likelihood approximations, and provides estimates of numerical standard error and relative numerical efficiency intrinsically. The paper concludes with an application that illustrates the potential of these simulators for applied Bayesian inference.

Numerical challenges inherent in algorithms for computing worst Value-at-Risk in homogeneous portfolios are identified and solutions as well as words of warning concerning their implementation are provided. Furthermore, both conceptual and computational improvements to the Rearrangement Algorithm for approximating worst Value-at-Risk for portfolios with arbitrary marginal loss distributions are given. In particular, a novel Adaptive Rearrangement Algorithm is introduced and investigated. These algorithms are implemented using the R package qrmtools.

The article is devoted to the problem of increase of efficiency of use of computer clusters with shared resources in the structure of the global informational Grіd System. It is proposed the adaptive model for control system of batch job processing of a cluster at alienation of its computing resources in conditions of presence of two competing flow of the entrance data

Herein the electromagnetic scattering is determined using the Finite Element Method. In particular the radar cross section of the scatterer is estimated. Comparison between the Finite Element Method (FEM), Method of Moments (MoM) and the method of Physical Optics (PO) is made in one numerical example. In another numerical example, the convergence rate is compared using pure h-refinement, p-enrichment and with a priori hp-adaptive refinements. The gain using the hp-adaptive approach is significant since an exponential convergence may be obtained.

Formal models of adaptive reconfiguration were developed. It allowed determining the value of the performance criteria of reconfigurable computing system. A new approach of reducing the critical execution time of parallel algorithms was proposed by removing reconfiguration time overheads from the critical path of algorithm`s graph. Program model of proposed means for adaptive tasks mapping on reconfigurable FPGA computing structure

Several tensor eigenpair definitions have been put forth in the past decade, but these can all be unified under generalized tensor eigenpair framework, introduced by Chang, Pearson, and Zhang (2009). Given mth-order, n-dimensional real-valued symmetric tensors A and B, the goal is to find $\lambda \in R$ and $x \in R^n$, $x \neq 0$, such that $Ax^{m-1} = \lambda Bx^{m-1}$. Different choices for B yield different versions of the tensor eigenvalue problem. We present our generalized eigenproblem adaptive power method (GEAP) method for solving the problem, which is an extension of the shifted symmetric higher-order power method (SS-HOPM) for finding Z-eigenpairs. A major drawback of SS-HOPM was that its performance depended in choosing an appropriate shift, but our GEAP method also includes an adaptive method for choosing the shift automatically.

We propose an adaptive version of the total variation algorithm proposed in [3] for computing the balanced cut of a graph. The algorithm from [3] used a sequence of inner total variation minimizations to guarantee descent of the balanced cut energy as well as convergence of the algorithm. In practice the total variation minimization step is never solved exactly. Instead, an accuracy parameter is specified and the total variation minimization terminates once this level of accuracy is reached. The choice of this parameter can vastly impact both the computational time of the overall algorithm as well as the accuracy of the result. Moreover, since the total variation minimization step is not solved exactly, the algorithm is not guarantied to be monotonic. In the present work we introduce a new adaptive stopping condition for the total variation minimization that guarantees monotonicity. This results in an algorithm that is actually monotonic in practice and is also significantly faster than previous, non-adaptive algorithms.

In a "publish-or-perish culture", the ranking of scientific journals plays a central role in assessing performance in the current research environment. With a wide range of existing methods and approaches to deriving journal rankings, meta-rankings have gained popularity as a means of aggregating different information sources. In this paper, we propose a method to create a consensus meta-ranking using heterogeneous journal rankings. Using a parametric model for paired comparison data we estimate quality scores for 58 journals in the OR/MS community, which together with a shrinkage procedure allows for the identification of clusters of journals with similar quality. The use of paired comparisons provides a flexible framework for deriving a consensus score while eliminating the problem of data missingness.

The design of a fully integrated adaptive modified complementary metal oxide-semiconductor (CMOS) synapse circuit is presented. By using multiple-gated transistor configuration in the modified CMOS synapse an additional branch provide control where the synaptic output current time constant is tuned. The effect of changing the multiple-gated transistor bias voltage from 0.25 to 0.45 V tunes the spiking output current exponential time-constant range by 200 ms as shown in simulation results. Moreover, a fully-integrated adaptive quadratic integrate-and-fire (QIF) CMOS neuron circuit is presented as well. A differential pair with variable capacitor integrator and a tunable schmitt trigger threshold detector circuit are integrated in the CMOS neuron that can be tuned varying its spiking frequency. The proposed adaptive quadratic integrate-and-fire (AQIF) neuron has the ability to adjust the spiking frequency without changing the input current. The simulation results show the proposed CMOS neuron circuit spiking frequency can be tuned from 58.4 to 312.5 Hz and its spiking period from 17.1 to 3.2 ms with tuning the bias voltage of variable capacitor integrator. Having a peak voltage Vpeak=0.95 V, a reset voltage Vreset=-0.75 V and a voltage threshold of 0.35 V with a membrane potential range of 1.5 V. The proposed CMOS neuron circuit is designed in 130 nm process with a supply voltage of 1.8 V and a total power dissipation of 1.8 mW.

Harmonic theory provides a mathematical framework to describe the structure, behavior, evolution and emergence of harmonic systems. A harmonic system is context aware, contains elements that manifest characteristics either collaboratively or independently according to system's expression and can interact with its environment. This theory provides a fresh way to analyze emergence and collaboration of "ad-hoc" and complex systems.

High order tensor arises more and more often in signal processing,data analysis, higher-order statistics, as well as imaging sciences. In this paper, an adaptive gradient (AG) method is presented for generalized tensor eigenpairs. Global convergence and linear convergence rate are established under some suitable conditions. Numerical results are reported to illustrate the efficiency of the proposed method. Comparing with the GEAP method, an adaptive shifted power method proposed by Tamara G. Kolda and Jackson R. Mayo [SIAM J. Matrix Anal. Appl., 35 (2014), pp. 1563-1581], the AG method is much faster and could reach the largest eigenpair with a higher probability.

Volunteer Computing, sometimes called Public Resource Computing, is an emerging computational model that is very suitable for work-pooled parallel processing. As more complex grid applications make use of work flows in their design and deployment it is reasonable to consider the impact of work flow deployment over a Volunteer Computing infrastructure. In this case, the inter work flow I/O can lead to a significant increase in I/O demands at the work pool server. A possible solution is the use of a Peer-to- Peer based parallel computing architecture to off-load this I/O demand to the workers; where the workers can fulfill some aspects of work flow coordination and I/O checking, etc. However, achieving robustness in such a large scale system is a challenging hurdle towards the decentralized execution of work flows and general parallel processes. To increase robustness, we propose and show the merits of using an adaptive checkpoint scheme that efficiently checkpoints the status of the parallel processes according to the estimation of relevant network and peer parameters. Our scheme uses statistical data observed during runtime to dynamically make checkpoint decisions in a completely de- centralized manner. The results of simulation show support for our proposed approach in terms of reduced required runtime.

We use ideas from distributed computing to study dynamic environments in which computational nodes, or decision makers, follow adaptive heuristics (Hart 2005), i.e., simple and unsophisticated rules of behavior, e.g., repeatedly "best replying" to others' actions, and minimizing "regret", that have been extensively studied in game theory and economics. We explore when convergence of such simple dynamics to an equilibrium is guaranteed in asynchronous computational environments, where nodes can act at any time. Our research agenda, distributed computing with adaptive heuristics, lies on the borderline of computer science (including distributed computing and learning) and game theory (including game dynamics and adaptive heuristics). We exhibit a general non-termination result for a broad class of heuristics with bounded recall---that is, simple rules of behavior that depend only on recent history of interaction between nodes. We consider implications of our result across a wide variety of interesting and timely applications: game theory, circuit design, social networks, routing and congestion control. We also study the computational and communication complexity of asynchronous dynamics and present some basic observations regarding the effects of asynchrony on no-regret dynamics. We believe that our work opens a new avenue for research in both distributed computing and game theory.

We use ideas from distributed computing to study dynamic environments in which computational nodes, or decision makers, follow adaptive heuristics (Hart 2005), i.e., simple and unsophisticated rules of behavior, e.g., repeatedly "best replying" to others' actions, and minimizing "regret", that have been extensively studied in game theory and economics. We explore when convergence of such simple dynamics to an equilibrium is guaranteed in asynchronous computational environments, where nodes can act at any time. Our research agenda, distributed computing with adaptive heuristics, lies on the borderline of computer science (including distributed computing and learning) and game theory (including game dynamics and adaptive heuristics). We exhibit a general non-termination result for a broad class of heuristics with bounded recall---that is, simple rules of behavior that depend only on recent history of interaction between nodes. We consider implications of our result across a wide variety of interesting and timely applications: game theory, circuit design, social networks, routing and congestion control. We also study the computational and communication complexity of asynchronous dynamics and present some basic observations regarding the effects of asynchrony on no-regret dynamics. We believe that our work opens a new avenue for research in both distributed computing and game theory.

We use ideas from distributed computing to study dynamic environments in which computational nodes, or decision makers, follow adaptive heuristics (Hart 2005), i.e., simple and unsophisticated rules of behavior, e.g., repeatedly "best replying" to others' actions, and minimizing "regret", that have been extensively studied in game theory and economics. We explore when convergence of such simple dynamics to an equilibrium is guaranteed in asynchronous computational environments, where nodes can act at any time. Our research agenda, distributed computing with adaptive heuristics, lies on the borderline of computer science (including distributed computing and learning) and game theory (including game dynamics and adaptive heuristics). We exhibit a general non-termination result for a broad class of heuristics with bounded recall---that is, simple rules of behavior that depend only on recent history of interaction between nodes. We consider implications of our result across a wide variety of interesting and timely applications: game theory, circuit design, social networks, routing and congestion control. We also study the computational and communication complexity of asynchronous dynamics and present some basic observations regarding the effects of asynchrony on no-regret dynamics. We believe that our work opens a new avenue for research in both distributed computing and game theory.

It has previously been shown that varying the numerical timestep during a symplectic orbital integration leads to a random walk in energy and angular momentum, destroying the phase space-conserving property of symplectic integrators. Here we show that when altering the timestep symplectic correctors can be used to reduce this error to a negligible level. Furthermore, these correctors can also be employed to avoid a large error introduction when changing the Hamiltonian's partitioning. We have constructed a numerical integrator using this technique that is nearly as accurate as widely used fixed-step routines. In addition, our algorithm is drastically faster for integrations of highly eccentricitic, large semimajor axis orbits, such as those found in the Oort Cloud.

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No abstract available

The Dynamic Reconfiguration for Adaptive Computing Systems (DRACS) effort has exploited the emerging technology associated with run-time reconfigurable devices to develop system capabilities for run-time reconfiguration (RTR) of AGS hardware both in response to software control and in a data-driven manner. Using the DARPA-sponsored GSRG dynamically reconfigurable device, DRAGS has demonstrated a host-driven design and reconfiguration as well as two data-driven designs, one Finite State Machine (FSM) driven and one additional host-driven demonstration. This report describes how these can be used to develop a virtual co-processor that supports multiple reconfigurable computing applications residing in a single piece of hardware. One demonstration focus selected involves a subset of a realistic system scenario for parameter measurement processing in electronic warfare that can be improved through the use of dynamic reconfiguration.

This Reconfigurable Computing (RC) or Adaptive Computing System (ACS) program focused on the development of both reconfigurable computing platforms and the associated programming support environments to demonstrate the viability of RC. This was demonstrated by exploring the ability to program RCs in a main/integrated C application program and by investigating new, partially reconfigurable technology. A Xilinx 4000 Field Programmable Gate Array (FPGA) series board and a Xilinx 6200 FPGA-based board were developed as pant of this effort. The C compiler technology was developed more for a hardware pragma-based implementation, which leveraged hardware macro libraries and worked quite effectively. The Xilinx 6200 board was interesting from the standpoint that the 6200 FPGAs are partially reconfigurable. The shortfalls of this product family include poor chip design/manufacture, resulting in the inability to utilize a good portion of the FPGA logic resources. Another shortfall is a lack of functional programming tools. In spite of these problems, the team was able to exercise the partial reconfigurability of the devices by developing programming tools of their own.

This report describes the activities of the DEFACTO project, a Design Environment for Adaptive Computing Technology funded under the DARPA Adaptive Computing Systems and Just-In-Time-Hardware programs. The goal of DEFACTO is to derive system-level implementations of mappings to FPGA-based systems, from a high-level algorithmic description in standard C. We have demonstrated synthesis time reductions to 100-10000X with the automated design space exploration algorithm. The current reduction in design time, including human effort, has been approximately 40-60X for two case studies, SLD from Sandia ATR and Sobel edge detection. We have demonstrated end-to-end mapping on the Annapolis Wildstar board for both examples, with no minimal intervention, at DarpaTech on 31 July 2002.

The General Computer Adaptive Test (CAT) of the Graduate Record Examinations (GRE) includes three operational sections that are separately timed and scored. A "no score" is reported if the examinee answers fewer than 80% of the items or if the examinee does not answer all of the items and leaves the section before time expires. The 80% threshold was adopted to set a minimum threshold to result in psychometrically acceptable scores without penalizing slow test takers. A study was conducted to examine the impact of possible CAT test-taking (and test completion) strategies and scoring options with regard to incomplete tests and to consider the impact of working to the 80% level or beyond it. Actual data for different completion points were selected from 70,000 GRE CAT examinees. CAT simulations were also conducted to assess the impact of different test taking strategies and different ways of scoring tests when not all items were answered. Data did not indicate that there is widespread use of the 80% rule as a strategy for deciding how much of the GRE CAT to complete. Serious psychometric and equity issues would be raised if examinees began to employ this strategy, so monitoring of examinee strategies is important. (Contains three figures and eight tables.) (SLD)

It is likely that NASA's future spacecraft systems will consist of distributed processes which will handle dynamically varying workloads in response to perceived scientific events, the spacecraft environment, spacecraft anomalies and user commands. Since all situations and possible uses of sensors cannot be anticipated during pre-deployment phases, an approach for dynamically adapting the allocation of distributed computational and communication resources is needed. To address this, we are evolving the DeSiDeRaTa adaptive resource management approach to enable reconfigurable ground and space information systems. The DeSiDeRaTa approach embodies a set of middleware mechanisms for adapting resource allocations, and a framework for reasoning about the real-time performance of distributed application systems. The framework and middleware will be extended to accommodate (1) the dynamic aspects of intra-constellation network topologies, and (2) the complete real-time path from the instrument to the user. We are developing a ground-based testbed that will enable NASA to perform early evaluation of adaptive resource management techniques without the expense of first deploying them in space. The benefits of the proposed effort are numerous, including the ability to use sensors in new ways not anticipated at design time; the production of information technology that ties the sensor web together; the accommodation of greater numbers of missions with fewer resources; and the opportunity to leverage the DeSiDeRaTa project's expertise, infrastructure and models for adaptive resource management for distributed real-time systems.

The article describes the issues of preparation and verification of mathematical models of computing systems with resource virtualization. The object of this study is to verify of mathematical models of computer systems with virtualization experimentally by creating a virtual server on the host platform and monitoring its characteristics under load. Known models cannot be applied to the aircraft with virtualization, because they do not allow a comprehensive analysis to determine the most effective option for the implementation of the initial allocation of resources and its optimization for a specific sphere and task of use. The article for the study used a closed queueing network. Simple models for the analysis of various structures of computer systems are experimentally obtained. To implement the properties of adaptability in the models, triggers are used that monitor and adjust the power of the processing channel in individual Queuing systems, depending on the specified conditions. Experiments prove the obtained results reliable and usable as a flexible tool for studying the virtualization properties when structuring computing systems. This knowledge could be of use for businesses interested in optimizing the server configuration for their IT infrastructure.

We present an efficient distributed memory parallel algorithm for computing connected components in undirected graphs based on Shiloach-Vishkin's PRAM approach. We discuss multiple optimization techniques that reduce communication volume as well as load-balance the algorithm. We also note that the efficiency of the parallel graph connectivity algorithm depends on the underlying graph topology. Particularly for short diameter graph components, we observe that parallel Breadth First Search (BFS) method offers better performance. However, running parallel BFS is not efficient for computing large diameter components or large number of small components. To address this challenge, we employ a heuristic that allows the algorithm to quickly predict the type of the network by computing the degree distribution and follow the optimal hybrid route. Using large graphs with diverse topologies from domains including metagenomics, web crawl, social graph and road networks, we show that our hybrid implementation is efficient and scalable for each of the graph types. Our approach achieves a runtime of 215 seconds using 32K cores of Cray XC30 for a metagenomic graph with over 50 billion edges. When compared against the previous state-of-the-art method, we see performance improvements up to 24x.

The goal of the Management System for Heterogeneous Networks (MSHN) is to provide a resource management system (RMS) to enable adaptive applications to use multiple sets of shared resources while accounting for dynamically changing priorities and environments. This RMS must be capable of providing each subscriber process with its required Quality of Service (which might include security considerations, deadlines, user priorities, and preferences) in a heterogeneous computing environment in which many processes are competing for shared resources. Applying this RMS technology to C4I modeling and simulation applications would enable on-scene Commanders to simulate complex elements of the decision process in order to optimize the use of forces and materiel. The objective of this thesis was to transparently intercept operating system calls made by a robust, C4I modeling application, the Extended Air Defense Simulation (EADSIM), in order to weigh the resources required against the confidence level of the outcomes obtained. Specifically, the goal was to determine resource usage required to run the application using both Monte Carlo simulation and deterministic simulation. MSHN needs this type of information to determine which version of an application to execute, in order to provide the best Quality of Service, while meeting operational deadlines

This article presents two novel adaptive-sparse polynomial dimensional decomposition (PDD) methods for solving high-dimensional uncertainty quantification problems in computational science and engineering. The methods entail global sensitivity analysis for retaining important PDD component functions, and a full- or sparse-grid dimension-reduction integration or quasi Monte Carlo simulation for estimating the PDD expansion coefficients. A unified algorithm, endowed with two distinct ranking schemes for grading component functions, was created for their numerical implementation. The fully adaptive-sparse PDD method is comprehensive and rigorous, leading to the second-moment statistics of a stochastic response that converges to the exact solution when the tolerances vanish. A partially adaptive-sparse PDD method, obtained through regulated adaptivity and sparsity, is economical and is, therefore, expected to solve practical problems with numerous variables. Compared with past developments, the adaptive-sparse PDD methods do not require its truncation parameter(s) to be assigned \emph{a priori} or arbitrarily. The numerical results reveal that an adaptive-sparse PDD method achieves a desired level of accuracy with considerably fewer coefficients compared with existing PDD approximations. For a required accuracy in calculating the probabilistic response characteristics, the new bivariate adaptive-sparse PDD method is more efficient than the existing bivariately truncated PDD method by almost an order of magnitude. Finally, stochastic dynamic analysis of a disk brake system was performed, demonstrating the ability of the new methods to tackle practical engineering problems.

The increased usage of smart phones has led to increase usage an internet based application services. These application requires different quality of service (QoS) and bandwidth requirement. WiMAX is an efficient network to provision high bandwidth connectivity and coverage to end user. To meet QoS requirement the exiting model used adaptive model selection scheme. However, these model induce bandwidth wastage as it does not considers any feedback information for scheduling. This work present an Adaptive Uplink Scheduling (AUS) by optimizing MAC layer using Multi-Objective Genetic Algorithm (MOGA). The MAC scheduler use feedback information from both physical layer and application layer. Further, to meet QoS requirement of application and utilize bandwidth efficiently this paper presented an adaptive modulation selection scheme based on user application requirement using MOGA. Our model provides application level based QoS provisioning for WiMAX network. Experiment are conducted to evaluate performance of AUS over exiting model. The overall result attained shows AUS model attain good performance in term of throughput, successful packet transmission and packet collision.

This report states the work performed by the Cameron project. The goal of the Cameron project is to make FPGAs and other adaptive computer systems available to more applications programmers, by raising the abstraction level from hardware circuits to software algorithms. To this end, we have developed a variant of the C programming language and an optimizing compiler that maps high-level programs directly onto FPGAs, and have tested the language and compiler on a variety of image processing (and other) applications. A high level language with its one step compiler for Adaptive Computing Systems has been designed and implemented, and the performance of DoD relevant applications has been analyzed on commercial off-the-shelf reconfigurable hardware.

This DURIP project was used to upgrade the computing capabilities of Rensselaer s Scientific Computation Research Center (SCOREC). The primary component is a parallel computing cluster with 22 Dell R620 compute nodes, each with two 8-core 2.6 GHz Intel Xeon processors (352 processors) and a direct connection to both a 56Gbps Infiniband fabric and a 10Gbps Ethernet fabric. To support the I/O demands storage arrays of 110 teraflops have been added to the SCOREC system. The last component is four workstations with an Intel Core i7 3.6 GHz 4-core processor and a Nvidia GTX580 graphics card.

"June 1999"

Numerical methods are developed for control of three dimensional adaptive test sections. The physical properties of the design problem occurring in the external field computation are analyzed, and a design procedure suited for solution of the problem is worked out. To do this, the desired wall shape is determined by stepwise modification of an initial contour. The necessary changes in geometry are determined with the aid of a panel procedure, or, with incident flow near the sonic range, with a transonic small perturbation (TSP) procedure. The designed wall shape, together with the wall deflections set during the tunnel run, are the input to a newly derived one-step formula which immediately yields the adapted wall contour. This is particularly important since the classical iterative adaptation scheme is shown to converge poorly for 3D flows. Experimental results obtained in the adaptive test section with eight flexible walls are presented to demonstrate the potential of the procedure. Finally, a method is described to minimize wall interference in 3D flows by adapting only the top and bottom wind tunnel walls.

Numerical methods are developed for control of three dimensional adaptive test sections. The physical properties of the design problem occurring in the external field computation are analyzed, and a design procedure suited for solution of the problem is worked out. To do this, the desired wall shape is determined by stepwise modification of an initial contour. The necessary changes in geometry are determined with the aid of a panel procedure, or, with incident flow near the sonic range, with a transonic small perturbation (TSP) procedure. The designed wall shape, together with the wall deflections set during the tunnel run, are the input to a newly derived one-step formula which immediately yields the adapted wall contour. This is particularly important since the classical iterative adaptation scheme is shown to converge poorly for 3D flows. Experimental results obtained in the adaptive test section with eight flexible walls are presented to demonstrate the potential of the procedure. Finally, a method is described to minimize wall interference in 3D flows by adapting only the top and bottom wind tunnel walls.

With the huge development in mobile and network fields, sensor technologies and fog computing help the students for more effective learning, flexible and in and effective manner from anywhere. Using the mobile device for learn encourage the transition to mobile computing (cloud and fog computing) which is led to the ability to design customized system that help student to learn via context aware learning which can be done by set the user preference and use proper methods to show only related manner subject.The presented study works on developing a system of e-learning which has been on the basis of fog computing concepts with deep learning approaches utilized for classification to the data content for accomplishing the context aware learning and use the adaptation of video quality using special equation and the data encrypted and decrypted using 3DES algorithm to ensure the security side of the operation.

With the huge development in mobile and network fields, sensor technologies and fog computing help the students for more effective learning, flexible and in and effective manner from anywhere. Using the mobile device for learn encourage the transition to mobile computing (cloud and fog computing) which is led to the ability to design customized system that help student to learn via context aware learning which can be done by set the user preference and use proper methods to show only related manner subject.The presented study works on developing a system of e-learning which has been on the basis of fog computing concepts with deep learning approaches utilized for classification to the data content for accomplishing the context aware learning and use the adaptation of video quality using special equation and the data encrypted and decrypted using 3DES algorithm to ensure the security side of the operation.

This project considered various sources of power consumption in general purpose high-performance and embedded processors and developed techniques for lowering the power consumption without significant sacrifice in performance. We have designed low power data caches and low power external data buses that can he used for both superscalar and embedded processors. For superscalar processors we have designed low complexity memory disambiguation mechanism, power efficient instruction issue mechanism, and load/store reuse techniques. For embedded processors we have developed techniques that allow us to achieve performance while operating on compacted code and data. The various techniques that were developed have been implemented as part of gcc compiler and the FAST simulation system. Experimentation was carried to demonstrate the utility of the techniques.

A new method for computing the resonant frequency of the circular microstrip antenna, based on the adaptive neuro-fuzzy inference system (ANFIS), is presented. A hybrid learning algorithm is used to identify the parameters of ANFIS. The results of the new method are in excellent agreement with the experimental results reported elsewhere.

This contract provided $143,500 from the AFOSR combined with $61,500 of cost sharing directly from Rensselaer Polytechnic Institute for the procurement of computer hardware to facilitate AFOSR sponsored research under the following research: (1) Large Eddy Simulation (LES) of turbulent flow over an airfoil using unstructured grids (Grant # F49620-97-1-0043) and (2) Crystal growth simulations and (3) parallel adaptive computations. To further leverage these fund they were combined with an additional $208,000 from a National Science Foundation research infrastructure grant (plus an additional $40,000 in Rensselaer matching for that grant) and an additional $138,000 from Silicon Graphics Inc. to purchase the following very substantial computational facility from Silicon Graphics Inc.: 1. 8 R10000 processors, 2. 3.5 Gigabytes shared memory (addressable by all processors), 3. 18 Gigabytes fast access hard disk, 4. Onyx2 InfiniteReality graphics engine, 5. 24 inch super-wide monitor, 6. Fakespace virtual reality stereoscopic visualization system (6' by 8' table with a 6' by 4.5' visualization surface that can be tilted to any angle), 7. Indigo2 workstation with 1 R10000 processor, 8. 320 Megabytes memory, 9. 9 Gigabytes hard disk, 10. Solid impact Graphics engine, 11. 20 inch Multi-Scan monitor.

The advantages of using DSP chips for high-performance embedded signal processing applications have been demonstrated during the past decade. However, it is now apparent that even DSP chips can be overkill for some computations found in common embedded military applications. This project investigates the advantages of integrating configurable hardware together with a multiprocessor DSP/GPP platform. The computational engine of the configurable hardware used in this project was comprised of FPGA chips. A primary goal of our project was to demonstrate that for given computational loads--associated with instances of embedded radar signal processing applications-the total size, weight, and power (SWAP) could be reduced by integrating FPGA-based components as part of the embedded computational platform.

The advantages of using DSP chips for high-performance embedded signal processing applications have been demonstrated during the past decade. However, it is now apparent that even DSP chips can be overkill for some computations found in common embedded military applications. This project investigates the advantages of integrating configurable hardware together with a multiprocessor DSP/GPP platform. The computational engine of the configurable hardware used in this project was comprised of FPGA chips. A primary goal of our project was to demonstrate that for given computational loads--associated with instances of embedded radar signal processing applications-the total size, weight, and power (SWAP) could be reduced by integrating FPGA-based components as part of the embedded computational platform.

This project consisted of the development of an adaptive computing system with an emphasis on remote sensor control, data acquisition, and sensor data processing. During the project, two hardware platforms were designed and developed and software was modified and extended to the new platforms. The developed hardware was then integrated into an existing infrared focal plan array sensor package and used for sensor control and data acquisition. The use of reconfigurable hardware has extended the capabilities of the sensor platform considerably and has proven very successful.

Adaptive Computing Systems (ACSs) can serve as flexible hardware accelerators for applications in domains such as image and signal processing. However, the mapping of applications onto ACSs using traditional methods can take months to develop and debug. To enable application designers to map their applications automatically, CHAMPION was developed to permit high-level design entry using the Khoros Cantata graphical programming environment and hide low-level details of the hardware architecture. The key idea underlying CHAMPION is its ability to reuse precompiled hardware modules written in VHDL. These modules produce identical results to fixed-point C modules installed in Cantata which the user interconnects graphically and simulates on a general purpose UNIX workstation. The resulting net-list is converted into a directed graph and manipulated by CHAMPION so that data widths and clock delays are matched. If the graph is too large for a single FPGA, then it is partitioned automatically. An automatic target recognition application was automatically mapped to a WildForce ACS containing five FPGAs, achieving a productivity gain of over 2000. Other moderately complex applications were mapped to multiple ACS platforms, as well as to single-chip ASICs. CHAMPION enables faster application development, ACSs to be utilized by a wider audience, and quick mapping onto multiple ACS platforms and ASICs, thereby exploiting rapid advances being made in hardware.

Architecture Adaptive Computing Environment (aCe) is a software system that includes a language, compiler, and run-time library for parallel computing. aCe was developed to enable programmers to write programs, more easily than was previously possible, for a variety of parallel computing architectures. Heretofore, it has been perceived to be difficult to write parallel programs for parallel computers and more difficult to port the programs to different parallel computing architectures. In contrast, aCe is supportable on all high-performance computing architectures. Currently, it is supported on LINUX clusters. aCe uses parallel programming constructs that facilitate writing of parallel programs. Such constructs were used in single-instruction/multiple-data (SIMD) programming languages of the 1980s, including Parallel Pascal, Parallel Forth, C*, *LISP, and MasPar MPL. In aCe, these constructs are extended and implemented for both SIMD and multiple- instruction/multiple-data (MIMD) architectures. Two new constructs incorporated in aCe are those of (1) scalar and virtual variables and (2) pre-computed paths. The scalar-and-virtual-variables construct increases flexibility in optimizing memory utilization in various architectures. The pre-computed-paths construct enables the compiler to pre-compute part of a communication operation once, rather than computing it every time the communication operation is performed.

A method and system for adapting fault tolerant computing. The method includes the steps of measuring an environmental condition representative of an environment. An on-board processing system's sensitivity to the measured environmental condition is measured. It is determined whether to reconfigure a fault tolerance of the on-board processing system based in part on the measured environmental condition. The fault tolerance of the on-board processing system may be reconfigured based in part on the measured environmental condition.

SLAAC assembled a multidisciplinary team with expertise in signal processing, design tools and adaptive architectures to develop distributed adaptive computing systems (ACS) and methodologies for Defense processing. SLAAC was organized around challenge applications that collectively guided the research, including: Synthetic Aperture Radar/Automatic Target Recognition (SAR/ATR), SONAR Beamforming, Wide-Band RF Receiver Processing Hyperspectral Image Processing, Electronic Counter Measures (ECM), and Infrared ATR. The challenges were selected to stress ACS systems in dimensions of computational density, memory bandwidth and latency, I/O bandwidth, and scalability. SLAAC had technology transitions in SAR, SONAR and ECM.

This effort addresses the challenge of bridging the gap between theory and practice by systematically developing design and implementation strategies to apply the generalized mathematical formulation of variable precision filters to configurable devices in adaptive computing machines. This effort will deliver a computer-aided design environment, based on commercial product that supports the design of variable precision filters for a given signal processing application as well as their implementation in an adaptive computing platform.