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A recently fabricated CMOS VLSI IC was designed to generate two-dimensional histograms in real-time on digital computers. This thesis reports the efforts to determine if the 2DHlST IC chip functions as designed. Tests were conducted with a logic analyzer, general purpose electronic test equipment, and circuit simulation software.

A recently fabricated CMOS VLSI IC was designed to generate two-dimensional histograms in real-time on digital computers. This thesis reports the efforts to determine if the 2DHlST IC chip functions as designed. Tests were conducted with a logic analyzer, general purpose electronic test equipment, and circuit simulation software. (MM)

Physical failure in LSI/VSLI circuits is highly dependent on the fabrication technology being used and result in a very complex faulty behavior. To reduce numbers and types of faults that must be handled for test generating and fault simulation, logic fault models are used. The most popular fault model is the single stuck line (SSL) which can emulate many common physical faults. Non-standard faults like short circuits are more difficult to model-usually require modification to the original circuit to allow use of SSL software. This approach is also ideal for handling Complementary Metal oxide Semiconductors faults. (Author)

We started the project by initiating a study of available literature that is related to the scope of work for this project. Testing of high complexity LSI and VLSI components has become very important, and has been receiving considerable interest. The project involves a test-effectiveness measure. Because of the complexity of the problem, it has not yet been satisfactorily approached by others. Some work on information theoretic approach has been reported, but the approach does not appear to be suitable for testing digital system with high fault coverage. We feel that test-effectiveness measure should be related with physically possible failures, and thus the measure should be available to use detailed information of the circuitry if it is available.

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy i.e. modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions etc, circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising. (Author)

Designing for testability if needed to reduce costs associated with testing and maintaining electronic systems. Two approaches are considered: (1) modification of established circuits and (2) general design of new circuits where testability is a major consideration. Computer programs TMEAS and SCOAP, developed for evaluating testability in established circuits, are discussed. In the design of new circuits only a few techniques are known that yield highly testable circuits without sacrificing other desirable traits, two, IBM's LSSD method and bit slicing, are discussed. (Author)

Designing for testability if needed to reduce costs associated with testing and maintaining electronic systems. Two approaches are considered: (1) modification of established circuits and (2) general design of new circuits where testability is a major consideration. Computer programs TMEAS and SCOAP, developed for evaluating testability in established circuits, are discussed. In the design of new circuits only a few techniques are known that yield highly testable circuits without sacrificing other desirable traits, two, IBM's LSSD method and bit slicing, are discussed. (Author)

Thesis advisor: Loomis, Jr., Hershel H

Thesis advisor: Loomis, Jr., Hershel H

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI (Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VLSI-based systems. This report is organized into two chapters. Chapter 1 presents the state-of-the-art for the functional testing of LSI/VLSI devices with special emphasis on microprocessor testing. Chapter 2 reports our new research results. We present three algorithms to test the instruction decoding function of microprocessors.

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI (Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VLSI-based systems. This report is organized into two chapters. Chapter 1 presents the state-of-the-art for the functional testing of LSI/VLSI devices with special emphasis on microprocessor testing. Chapter 2 reports our new research results. We present three algorithms to test the instruction decoding function of microprocessors.

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI (Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VLSI-based systems. This report is organized into two chapters. Chapter 1 presents the state-of-the-art for the functional testing of LSI/VLSI devices with special emphasis on microprocessor testing. Chapter 2 reports our new research results. We present three algorithms to test the instruction decoding function of microprocessors.

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine- McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine- McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine- McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: ̲= tan-1(Q/I). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined within this thesis. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

The study of radiation effects on VLSI components is a very heavily researched topic. There are several reasons for this research, one of which is the application of VLSI components to space related vehicles. One component essential to Analog VLSI elements is the capacitor. The purpose of this paper is to better define the actual effects of radiation on the MOS VLSI capacitor. The radiation testing is conducted using the NPS electron linear accelerator. The data is taken while the capacitor is being exposed to an accumulating dose of electron radiation. The capacitance values are monitored using the parameter changes of a specially designed low pass filter circuit. The 3 dB breakpoint frequency of this filter is used to calculate the actual capacitance. The capacitance value is then related to the accumulated radiation dose in Rads. The results are very important and needed, especially if off-the-shelf components are to be utilized in the design of spacecraft systems.

The study of radiation effects on VLSI components is a very heavily researched topic. There are several reasons for this research, one of which is the application of VLSI components to space related vehicles. One component essential to Analog VLSI elements is the capacitor. The purpose of this paper is to better define the actual effects of radiation on the MOS VLSI capacitor. The radiation testing is conducted using the NPS electron linear accelerator. The data is taken while the capacitor is being exposed to an accumulating dose of electron radiation. The capacitance values are monitored using the parameter changes of a specially designed low pass filter circuit. The 3 dB breakpoint frequency of this filter is used to calculate the actual capacitance. The capacitance value is then related to the accumulated radiation dose in Rads. The results are very important and needed, especially if off-the-shelf components are to be utilized in the design of spacecraft systems.

Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT techniques of Scan Path and Built in Test are described. An engineering methodology that uses the Genesil Silicon Compiler to produce a VLSI design, DFT-CHIP, which utilizes the DFT Scan Path technique is presented. Included are the procedures for using Genesil's simulation, timing analysis and automatic test generation features. The steps taken to fabricate the DFT-CHIP design through MOSIS are discussed. The methodology used to test the fabricated DFT- CHIP design on the Tektronix DAS 9100 tester is described. Appendix A and Appendix B provide copies of the Genesil check functions written for use during simulation on the DFT-CHIP design. Appendix C specifies the Genesil timing information for the DFT-CHIP design. Appendix D lists the conversion program which translates Genesil produced test vector files to the file format used during testing on the Tektronix tester.

This contract investigated several new technologies useful for real- time internal node probing of VLSI integrated circuits. Electro-optic, electroabsorptive, photoconductive, and magnetic probe technologies were studied, and their relative merits and drawbacks compared. Testing parameters were less than or equal to 5ns temporal resolution, less than or equal to 50 mV sensitivity, and less than or equal to 2 spatial resolution. Both theoretical and experimental work was performed. Conclusions are drawn indicating the most promising candidates for future in-depth studies.

The demands for higher system reliability and self checking required by the new fault tolerant computers have put new emphais on the use of the redundant circuits. Types of redundancy include parallel, triple modular redundancy, Quadd, standby, hybrid and software. Various computers employing one or more of these types are discussed. Generally, hardware, software and time redundancy required for error detection and correltion, are interrelated. Mathematical modleing, when applied to fault tolerant systems, can be used to measure the system reliability.

The demands for higher system reliability and self checking required by the new fault tolerant computers have put new emphais on the use of the redundant circuits. Types of redundancy include parallel, triple modular redundancy, Quadd, standby, hybrid and software. Various computers employing one or more of these types are discussed. Generally, hardware, software and time redundancy required for error detection and correltion, are interrelated. Mathematical modleing, when applied to fault tolerant systems, can be used to measure the system reliability.

The demands for higher system reliability and self checking required by the new fault tolerant computers have put new emphais on the use of the redundant circuits. Types of redundancy include parallel, triple modular redundancy, Quadd, standby, hybrid and software. Various computers employing one or more of these types are discussed. Generally, hardware, software and time redundancy required for error detection and correltion, are interrelated. Mathematical modleing, when applied to fault tolerant systems, can be used to measure the system reliability.

The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

Thesis advisor(s): Sherif Michael

Thesis advisor(s): Sherif Michael

Thesis advisor(s): Sherif Michael

This paper presents a method for functional testing of microprocessors. First, we develop a control fault model at the RTL (Register Transfer Language) level. Based on this model, we establish testing requirements for control faults. We present three test procedures to verify the write and read sequences and use the write and read sequences to test other instructions in a microprocessor. By utilizing k-out-of-m codes, we can use fewer tests to cover more faults, thereby reducing the test generation time. (Author)

This project is a two-phase study dealing with testing and testability of custom LSI/VLSI circuits. The tasks summarized and evaluated in this report consisted of compiling and documenting a survey and assessment of the state-of-the-art for each of seven topics. Each of these topics has resulted in a formal report and are listed below: Vol. 2: Hardware Design Verification; Vol. 3: Fault Mode Analysis; Vol. 4: Test Generation; Vol. 5: Design for Testability; Vol. 6: Redundancy, Testing Circuits, and Codes; Vol. 7: Built-in Testing (BIT) and Built-in Test Equipment (BITE); and Vol. 8: Fault Simulation.

Two major approaches are considered for generating tests for digital systems: methods based on detailed circuit models of the unit under test (UUT) and methods based primarily on a functional description of the UUT. In addition to test generation of general digital systems, the testing requirements of microprocessors, semiconductor memories and PLA are examined. The D-algorithm and several variants are discussed as a basis for practical test generation procedures. (Author)

Two major approaches are considered for generating tests for digital systems: methods based on detailed circuit models of the unit under test (UUT) and methods based primarily on a functional description of the UUT. In addition to test generation of general digital systems, the testing requirements of microprocessors, semiconductor memories and PLA are examined. The D-algorithm and several variants are discussed as a basis for practical test generation procedures. (Author)

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI(Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VSLI-based systems. As a result of the rapidly increasing complexity of modern digital LSI/VLSI systems, functional testing is attracting more attention than ever not only in the computer manufacturing industry but also in the diversified potential applications. Functional testing uses a representation of a digital system higher than the gate-level testing. In functional testing, functional faults with respect to the functional specification (e.g., addition operation in a processor) are tested instead of a signal faults (e.g., a line stuck-at logical 0) in the circuit representation. The purpose of functional testing is to validate correct functional operations of digital systems according to their specifications.

Microprocessor is a type of complex sequential machine. The current approach is to test microprocessor by instruction execution. Generally, before executing an instruction-under-test, we have to write certain data into some registrers, and after executing the instruction, we have to read the contents of the registers. Therefore, if the write or read instruction is faulty, we may not be able to test the instruction-under-test. To solve this problem, Thatte and Abraham have to label instructions and define test order in detail before testing. In addition, they do not consider the partial execution of an instruction. So one of the instruction decoding faults I(j)/I(j)+I(k) is assumed that, instead of executing I(j), both insructions I(j) and I(k) are executed to completion. This raises the problem of practicality. Abraham and Packer's method is simple, but their 'register read' test procedure does not guarantee the correctness of write and read register functions for any data. In our work, we consider the write and read register function as a kernel of a microprocessor; similar to a sequential machine, and we use the checking experiment to verify the kernal based on the fault models. Then we use the kernal for testing other instructions. Our approach consists of three steps: Step 1: Establish the fault model for representing functional faults, Step 2: Determine the requirement for test generation, and Step 3: Based on the requirements, develop testing mprocedures.

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined within this thesis. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Functional testing is a feasible solution for LSI/VLSI test generation and design verification. In this paper, we present a systematic way to perform functional testing using an advanced symbolic execution technique. Symbolic execution is a very useful and powerful software engineering technique mainly used in program analysis including test generation. Often a single symbolic execution of a program may represent a large number of normal test runs.

We present the details of the design, simulation, construction, and testing of the VLSI-PLM Board. The VLSI-PLM Board is a wire-wrapped processor board for the VLSI-PLM Chip, a high performance CMOS processor for executing computer programs written in the Prolog language. All work was performed at the University of California at Berkeley. The design and simulations were performed using Mentor Graphics Computer Aided Design (CAD) tools on Apollo workstations. By using these tools, we were able to draw the gate-level design schematics on the computer and simulate the functionality and timing of the design. After the gate-level design passed all simulation tests, a wire-wrapped board was constructed with assistance from the Electronics Research Lab of the Electrical Engineering and Computer Science (EECS) Department. This wire-wrapped board was tested using a custom-made tester panel. The wire-wrapped board tests verified the computer simulations of the gate-level design. The total wire-wrapped part occupies 18 cm by 22 cm in a board 40 cm by 36 cm, with a total of 95 Integrated Circuit (IC) chips including the VLSI-PLM Chip.

The study of radiation effects on VLSI components is a very heavily researched topic. There are several reasons for this research, one of which is the application of VLSI components to space related vehicles. One component essential to Analog VLSI elements is the capacitor. The purpose of this paper is to better define the actual effects of radiation on the MOS VLSI capacitor. The radiation testing is conducted using the NPS electron linear accelerator. The data is taken while the capacitor is being exposed to an accumulating dose of electron radiation. The capacitance values are monitored using the parameter changes of a specially designed low pass filter circuit. The 3 dB breakpoint frequency of this filter is used to calculate the actual capacitance. The capacitance value is then related to the accumulated radiation dose in Rads. The results are very important and needed, especially if off-the-shelf components are to be utilized in the design of spacecraft systems.

The use of Linear Feedback Shift Register functions in generating exhaustive test case coverage for Very Large Scale Integrated circuits with SCAN/SET capability is presented. Both deterministic and probabilistic approaches to test pattern generation are discussed. A technique for signature generation is presented with analysis of its effectiveness. Also, a technique is described for consolidating the test patttern generation and signature capture functions into a single test/detect capability that requires less built-in hardware for implementation.

Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT techniques of Scan Path and Built in Test are described. An engineering methodology that uses the Genesil Silicon Compiler to produce a VLSI design, DFT-CHIP, which utilizes the DFT Scan Path technique is presented. Included are the procedures for using Genesil's simulation, timing analysis and automatic test generation features. The steps taken to fabricate the DFT-CHIP design through MOSIS are discussed. The methodology used to test the fabricated DFT- CHIP design on the Tektronix DAS 9100 tester is described. Appendix A and Appendix B provide copies of the Genesil check functions written for use during simulation on the DFT-CHIP design. Appendix C specifies the Genesil timing information for the DFT-CHIP design. Appendix D lists the conversion program which translates Genesil produced test vector files to the file format used during testing on the Tektronix tester.

Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT techniques of Scan Path and Built in Test are described. An engineering methodology that uses the Genesil Silicon Compiler to produce a VLSI design, DFT-CHIP, which utilizes the DFT Scan Path technique is presented. Included are the procedures for using Genesil's simulation, timing analysis and automatic test generation features. The steps taken to fabricate the DFT-CHIP design through MOSIS are discussed. The methodology used to test the fabricated DFT- CHIP design on the Tektronix DAS 9100 tester is described. Appendix A and Appendix B provide copies of the Genesil check functions written for use during simulation on the DFT-CHIP design. Appendix C specifies the Genesil timing information for the DFT-CHIP design. Appendix D lists the conversion program which translates Genesil produced test vector files to the file format used during testing on the Tektronix tester.

The author has studied thoroughly the fundamental contributions made by Thatte and Abraham who have considered the problem of micro-processor testing, Based on the architecture information available to a user and the instruction set for a given microprocessor, they define a graph model of the microprocessor under consideration. This model is then used to derive necessary tests. Their approach is, first to label the nodes and edges in the graph based on the observability of such nodes and edges. The faults are divided into five different classes namely register decoding, instruction decoding/control, data path, data storage and data manipulation faults. Explicit models are given for all these fault classes and functional units. It is assumed that no more than one functional unit is faulty, though any number of faults of one class can be present. Procedures are then developed to detect faults of different classes. They have also studied the fault coverage of their tests for a Hewlett Packard system.

This paper presents a number of algorithms to test the instruction decoding function of microprocessors based on some timing and control information available to users. Keywords: Register Transfer Language; Digital Networks.

This paper presents a number of algorithms to test the instruction decoding function of microprocessors based on some timing and control information available to users. Keywords: Register Transfer Language; Digital Networks.

This paper presents a number of algorithms to test the instruction decoding function of microprocessors based on some timing and control information available to users. Keywords: Register Transfer Language; Digital Networks.