Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits - Info and Reading Options
By David M. Russinoff
"Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits" was published by National Aeronautics and Space Administration, Langley Research Center in 1995 - Hampton, Va and the language of the book is English.
“Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits” Metadata:
- Title: ➤ Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits
- Author: David M. Russinoff
- Language: English
- Publisher: ➤ National Aeronautics and Space Administration, Langley Research Center
- Publish Date: 1995
- Publish Location: Hampton, Va
“Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits” Subjects and Themes:
- Subjects: Hardware description languages - VHSIC (Circuits) - Mathematical models - Program verification (Computers) - Protocol (Computers)
Edition Specifications:
- Format: Microform
- Pagination: 1 v.
Edition Identifiers:
- The Open Library ID: OL17788793M - OL11554233W
- Online Computer Library Center (OCLC) ID: 32874928
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