Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits - Info and Reading Options
By David M. Russinoff
“Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits” Metadata:
- Title: ➤ Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits
- Author: David M. Russinoff
“Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits” Subjects and Themes:
- Subjects: Hardware description languages - VHSIC (Circuits) - Mathematical models - Program verification (Computers) - Protocol (Computers)
Edition Identifiers:
- The Open Library ID: OL11554233W
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