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Multiple Valued Programmable Logic Array Minimization By Simulated Annealing by Gerard W. Dueck
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1Multiple-valued programmable logic array minimization by simulated annealing
By Gerard W. Dueck
“Multiple-valued programmable logic array minimization by simulated annealing” Metadata:
- Title: ➤ Multiple-valued programmable logic array minimization by simulated annealing
- Author: Gerard W. Dueck
- Language: English
- Number of Pages: Median: 27
- Publisher: ➤ Naval Postgraduate School - Available from National Technical Information Service
- Publish Date: 1992
- Publish Location: ➤ Springfield, Va - Monterey, Calif
“Multiple-valued programmable logic array minimization by simulated annealing” Subjects and Themes:
- Subjects: ANNEALING - COMPUTER AIDED DESIGN - COMPUTERIZED SIMULATION - LOGIC CIRCUITS - COMPUTER PROGRAMS
Edition Identifiers:
- The Open Library ID: OL33193246M
Access and General Info:
- First Year Published: 1992
- Is Full Text Available: Yes
- Is The Book Public: Yes
- Access Status: Public
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