Proceedings - Info and Reading Options

"Proceedings" Table Of Contents:

• 1- Matching memory to the power of personal computers / R. Foss
• 2- A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.]
• 3- High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.]
• 4- An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev
• 5- SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen
• 6- False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley
• 7- A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker
• 8- Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant
• 9- A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao
• 10- A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.]
• 11- Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang
• 12- An open notation for memory tests / A. Offerman, A. van de Goor
• 13- Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.]
• 14- Memory array testing through a scannable configuration / S. Yano, N. Ishiura
• 15- A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.].

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