Proceedings - Info and Reading Options
International Workshop on Memory Technology, Design, and Testing
By IEEE International Workshop on Memory Technology, Design, and Testing (1997 San Jose, Calif.)
"Proceedings" was published by IEEE Computer Society Press in 1997 - Piscataway, N.J., it has 103 pages and the language of the book is English.
“Proceedings” Metadata:
- Title: Proceedings
- Author: ➤ IEEE International Workshop on Memory Technology, Design, and Testing (1997 San Jose, Calif.)
- Language: English
- Number of Pages: 103
- Publisher: IEEE Computer Society Press
- Publish Date: 1997
- Publish Location: Piscataway, N.J.
“Proceedings” Subjects and Themes:
- Subjects: Congresses - Semiconductor storage devices - Testing - Random access memory
Edition Specifications:
- Format: Unknown Binding
Edition Identifiers:
- The Open Library ID: OL11390453M - OL1685355W
- ISBN-13: ➤ 9780818681004 - 9780818681011 - 9780818684944 - 9780818684968 - 9780769512426 - 9780769512433 - 9780769512440 - 9780818680991
- ISBN-10: 0818681004
- All ISBNs: ➤ 0818681004 - 9780818681004 - 9780818681011 - 9780818684944 - 9780818684968 - 9780769512426 - 9780769512433 - 9780769512440 - 9780818680991
AI-generated Review of “Proceedings”:
"Proceedings" Description:
Open Data:
Annotation, The 14 papers in this collection from the August 2001 workshop are divided into five sessions on semiconductor memory design, BIST, redundancy and error control, fault models and multi-port SRAM testing, and verification and testing. Some of the topics are evaluation of redundancy analysis algorithms, a parallel approach for testing multi-port static random access memories, a low output resistance charge pump for flash memory programming, BIST-based bitfail mapping of an embedded DRAM, and an orthogonal transpose- RAM cell array architecture with an alternate bit-line to bit-line contact scheme. No subject index. c. Book News Inc
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