Electromigration Modeling at Circuit Layout Level - Info and Reading Options
By Cher Ming Tan
"Electromigration Modeling at Circuit Layout Level" was published by Springer Singapore in 2013 - Singapore, it has 103 pages and the language of the book is English.
“Electromigration Modeling at Circuit Layout Level” Metadata:
- Title: ➤ Electromigration Modeling at Circuit Layout Level
- Author: Cher Ming Tan
- Language: English
- Number of Pages: 103
- Publisher: Springer Singapore
- Publish Date: 2013
- Publish Location: Singapore
“Electromigration Modeling at Circuit Layout Level” Subjects and Themes:
- Subjects: ➤ Engineering - Quality Control, Reliability, Safety and Risk - Electronic Circuits and Devices - System safety - Atomic, Molecular, Optical and Plasma Physics - Integrated circuits - Diffusion
Edition Specifications:
- Format: [electronic resource] /
- Pagination: ➤ IX, 103 p. 75 illus., 2 illus. in color.
Edition Identifiers:
- The Open Library ID: OL27034979M - OL19846014W
- ISBN-13: 9789814451215
- All ISBNs: 9789814451215
AI-generated Review of “Electromigration Modeling at Circuit Layout Level”:
"Electromigration Modeling at Circuit Layout Level" Table Of Contents:
- 1- Introduction
- 2- 3D Circuit Model Construction and Simulation
- 3- Comparison of EM Performance in Circuit Structure and Test Structure
- 4- Interconnect EM Reliability Modeling at Circuit Layout Level
- 5- Conclusion.
"Electromigration Modeling at Circuit Layout Level" Description:
The Open Library:
Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.
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