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This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: ̲= tan-1(Q/I). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: ̲= tan-1(Q/I). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

A system of custom cell building blocks utilizing scaleable CMOS technology is decribed. The cells are design to support the high speed, pipelined addition, subtraction, and multiplication operations neccessary in a cyclic spectral analyser or other applications involving the FFT. The cells are structured in such a manner as to permit a designer to tailor the bit-length of the operations and the number of pipline stages used. Both fixed and floating operations are supported by the system. The size and performance characteristics of devices produced using the cells are compared with previously produced Genesil Silicon Complier pipelined desings. The appendix contains designs of 16-bit mantissa, 12-bit exponent floating point multiplier and adder produced from the standard cells. If fabricated in 1.2(symbol) feature size technology, the theoretical maximum clock speed and throughput rate is 102 MHz with an asymmetric clock and 61 MHz using a symmetric clock waveform. Devices with clock speeds up to 178 MHz are possible if the number of logic cells between a pipeline stage is reduced to one

A system of custom cell building blocks utilizing scaleable CMOS technology is decribed. The cells are design to support the high speed, pipelined addition, subtraction, and multiplication operations neccessary in a cyclic spectral analyser or other applications involving the FFT. The cells are structured in such a manner as to permit a designer to tailor the bit-length of the operations and the number of pipline stages used. Both fixed and floating operations are supported by the system. The size and performance characteristics of devices produced using the cells are compared with previously produced Genesil Silicon Complier pipelined desings. The appendix contains designs of 16-bit mantissa, 12-bit exponent floating point multiplier and adder produced from the standard cells. If fabricated in 1.2(symbol) feature size technology, the theoretical maximum clock speed and throughput rate is 102 MHz with an asymmetric clock and 61 MHz using a symmetric clock waveform. Devices with clock speeds up to 178 MHz are possible if the number of logic cells between a pipeline stage is reduced to one

This is the supplemental disk to "VLSI Design and Hardware Description Languages", an advanced-undergraduate/graduate level introduction to VLSI chip design with the HDL Verilog, which includes full code listings for the book. The core project of this book is the implementation of a RISC-family/MIPS-ish processor, ready for tapeout to physical silicon. This book describes the methodology used to design and implement this processor, including co-simulation between a high-level interpreter model along with an HDL model, as well as processor testing on a physical chip.  The unpacked archive "1_TO_4.ZIP" contains the following sections. 1  VERILOG Examples This section contains the VERILOG examples of Chapter 11 of the book. It  supports computer aided searching and own simulations. 2  Interpreter Model This is the complete VERILOG model of the RISC processor TOOBSIE on the behavior  level. It serves as a reference for the instruction set. 3  Coarse Structure Model This is the complete VERILOG model of the RISC processor TOOBSIE on the register  transfer level and below. 4  Operating System and Examples The operating system VOS supports more comfortable experiments with the Coarse  Structure Model. For this purpose, there are also example application programs.  This section, however, does not belong to the actual target of the book.

Automated Test Station for VLSI (ATV) is a system design to ascertain correct functioning of a VLSI circuit. It is intended to test an Integrated Circuit (VLSI) by using Standard IC Tester, (developed at Standford University, California). The tester has the capability of addressing, simulating, and measuring status of any pin of its test connector, to which an ICUT (IC Under Test) is attached. The test vectors to simulate the ICUT and reference data to analyze the response of an ICUT are extracted from ESIM files in VAX-11/780 computer system and stored on 8 in. floppy disks to be utilized with microcomputer. These ESIM files, typically produced during Computer Aided Design phase of a VLSI circuit, contain node data generated during its simulator run. The LSI-11/23 microcomputer will be used to control the functions of IC tester and provide test and reference data. The user will have the capability to guide the course of operation by selecting various operating options in an interactive manner. Originator-supplied keywords include: VLSI testing; Microcomputer; and Computer programs.

This study explores the idea of building a library of VHDL con gurable components for use in digital radar applications. Con gurable components allows a designer to choose which components he or she needs and con gures those components for a speci c application. By doing this, design time for ASICs and FPGAs is shortened because the components are already designed and tested. This idea is demonstrated with a con gurable dynamic pipelinable fast fourier transform. Many FFT implementations exist, but this implementation is both con gurable and dynamic. Pre-synthesis customization allows the FFT to be tailored to almost any DSP application, and the dynamic property allows the FFT to calculate di erent length FFTs run-time. Three objectives will be accomplished: design and characterization of the aforementioned FFT; analysis of the error involved in the FFT calculation using di erent twiddle factor bit widths; and nally an analysis of all the con gurations for the synthesized design using a 90nm technology library. Speeds of up to 225 MHz have been simulated for a length-1024 FFT using the 90 nm technology.

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Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

The goal of this project is to redesign, fabricate, and assemble a digital circuit operating near a frequency of 250 MHz to test a new experimental Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM). This thesis presents the redesigned six-layer printed circuit test fixture and the design of the DRAM hold down clamp necessary to affix the DRAM to the test fixture. The use of commercially available Computer Aided Design (CAD) and Computer Aided Manufacturing CAM) tools were used for layout and fabrication. Finally, the assembly and testing of the test fixture, as well as problems encountered during the redesign, fabrication, and assembly processes, are discussed.

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

Abstract An essential component of promoting innovation and dependability in contemporary electronic systems is the pursuit of improved prediction accuracy in the field of very large-scale integration (VLSI) circuit design. However, the problem of inadequate data frequently arises in the traditional design routes, making it difficult to achieve the appropriate level of precision. To improve the accuracy of future machine learning models in activities like performance evaluation, design, and testing—where training data is typically known to be very limited— this work explores the use of diffusion models to generate false data for electrical circuits. To support our suggested diffusion model, we conduct simulations in the HSPICE design environment using 22nm CMOS technology nodes to get real-world training data that is typical of the situation. Our findings show that data generated artificially via diffusion model closely resembles genuine data. We confirm the accuracy of the produced data and show that data augmentation is definitely useful for digital circuit VLSI design prediction analysis. Citation: Khetarpal, V. (2024). Improving Predictive Accuracy In VLSI Circuit Design With Synthetic Data Generation. International Journal of Applied and Behavioral Sciences , 01 (01), 21–28. https://doi.org/10.70388/ijabs24703

Abstract An essential component of promoting innovation and dependability in contemporary electronic systems is the pursuit of improved prediction accuracy in the field of very large-scale integration (VLSI) circuit design. However, the problem of inadequate data frequently arises in the traditional design routes, making it difficult to achieve the appropriate level of precision. To improve the accuracy of future machine learning models in activities like performance evaluation, design, and testing—where training data is typically known to be very limited— this work explores the use of diffusion models to generate false data for electrical circuits. To support our suggested diffusion model, we conduct simulations in the HSPICE design environment using 22nm CMOS technology nodes to get real-world training data that is typical of the situation. Our findings show that data generated artificially via diffusion model closely resembles genuine data. We confirm the accuracy of the produced data and show that data augmentation is definitely useful for digital circuit VLSI design prediction analysis. Citation: Khetarpal, V. (2024). Improving Predictive Accuracy In VLSI Circuit Design With Synthetic Data Generation. International Journal of Applied and Behavioral Sciences , 01 (01), 21–28. https://doi.org/10.70388/ijabs24703

Abstract An essential component of promoting innovation and dependability in contemporary electronic systems is the pursuit of improved prediction accuracy in the field of very large-scale integration (VLSI) circuit design. However, the problem of inadequate data frequently arises in the traditional design routes, making it difficult to achieve the appropriate level of precision. To improve the accuracy of future machine learning models in activities like performance evaluation, design, and testing—where training data is typically known to be very limited— this work explores the use of diffusion models to generate false data for electrical circuits. To support our suggested diffusion model, we conduct simulations in the HSPICE design environment using 22nm CMOS technology nodes to get real-world training data that is typical of the situation. Our findings show that data generated artificially via diffusion model closely resembles genuine data. We confirm the accuracy of the produced data and show that data augmentation is definitely useful for digital circuit VLSI design prediction analysis. Citation: Khetarpal, V. (2024). Improving Predictive Accuracy In VLSI Circuit Design With Synthetic Data Generation. International Journal of Applied and Behavioral Sciences , 01 (01), 21–28. https://doi.org/10.70388/ijabs24703

There are eleven Georgia Tech VLSI designs in the AHAT Program. Each of these designs has been produced by Georgia Tech using the Genesil Silicon Compiler. Each design has passed the design verification process at Silicon Compiler Systems I Mentor Graphics and each has been fabricated in a bulk CMOS process (fabrication of certain chips was not complete when this document was released). Each of the Georgia Tech designs listed in Table 1 is being delivered to USASDC and to the Harris Corporation for conversion and fabrication in a rad-hard process. The program under which this work is done is AHAT (Advanced Hardened Avionics Technology). This document includes design information for the Georgia Tech instruction address generation chip, GT-VIAG.

Continuing work on thermal oxidation of silicon (at pressures to 20 atm) is discussed along with work on ion implantation (Boltzman transport modeling, range statistics, and record mechanisms). CVD and silicide technology, interface physics, and the continuing development of the STANFORD SUPREM process modeling program.

Continuing work on thermal oxidation of silicon (at pressures to 20 atm) is discussed along with work on ion implantation (Boltzman transport modeling, range statistics, and record mechanisms). CVD and silicide technology, interface physics, and the continuing development of the STANFORD SUPREM process modeling program.

Topics reported include: Task 1--Consultation from fabrication lines, CMOS-SOS and NMOS-Si gate test-chips, Geometrical design rules, Speed and timing rules, and Testability rules; and Task 2--CIF/APPLICON, CALMA conversion software, and Circuit design.

From the bitsavers.org collection, a scanned-in computer-related document. magazine :: VLSI Systems Design :: VLSI Systems Design V09 N02 198802

From the bitsavers.org collection, a scanned-in computer-related document. magazine :: VLSI Systems Design :: VLSI Systems Design V09 N02 198802

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

There are eleven Georgia Tech VLSI designs in the AHAT Program. Each of these designs has been produced by Georgia Tech using the Genesil Silicon Compiler. Each design has passed the design verification process at Silicon Compiler Systems I Mentor Graphics and each has been fabricated in a bulk CMOS process (fabrication of certain chips was not complete when this document was released). Each of the Georgia Tech designs listed in Table 1 is being delivered to USASDC and to the Harris Corporation for conversion and fabrication in a rad-hard process. The program under which this work is done is AHAT (Advanced Hardened Avionics Technology). This document includes design information for the Georgia Tech data address generation chip, GT-VDAG.

The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

Standard cell placement is a NP complete open problem. The main objectives of a placement algorithm are to minimize chip area and the total wire length of all the nets. Due to interconnect dominance, Deep Sub Micron VLSI design flow does not converge leading to iterations between synthesis and layout steps. We present a new heuristic placement algorithm called Sankeerna, which tightly couples synthesis and routing and produces compact routable designs with minimum area and delay. We tested Sankeerna on several benchmarks using 0.13 micron, 8 metal layer, standard cell technology library. There is an average improvement of 46.2% in delay, 8.8% in area and 114.4% in wire length when compared to existing placement algorithms. In this paper, we described the design and implementation of Sankeerna algorithm and its performance is illustrated through a worked out example.

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The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

This report describes the accomplishments during the contract period (March 27, 1990 to March 26, 1991) on the computer-aided analysis of CMOS device and circuit degradation due to hot-electron effects. The task involved four subtasks: (1) modeling of the gate oxide degradation in n-channel MOS transistor; (2) modeling of n-channel MOS transistor behavior with localized oxide damage; (3) simulation of gate oxide degradation during long-term circuit operation; (4) determination of overall circuit performance after hot-electron stress. For the modeling of the gate oxide degradation in nMOS transistor, a localized triangular charged density distribution function has been introduced in the drain end of the channel. This model was effective in explaining the local electric potential near the drain, especially on the flatband voltage and also the changes in the local channel electron mobility. To model the behavior of nMOS transistor with local oxide damages, a new one-dimensional I-V equation has been derived and implemented in a generic circuit simulator, iSMILE program. For the modeling of gate oxide degradation process, the rate equations governing the generation of interface states have been implemented for dynamic circuit operating conditions. With these mechanisms implemented, the iSMILE program has been able to simulate the degradation of circuit performances dynamically. For large scale reliability simulation, simpler models have been devised and used in the iDSIM2 program.

This report describes the accomplishments during the contract period (March 27, 1990 to March 26, 1991) on the computer-aided analysis of CMOS device and circuit degradation due to hot-electron effects. The task involved four subtasks: (1) modeling of the gate oxide degradation in n-channel MOS transistor; (2) modeling of n-channel MOS transistor behavior with localized oxide damage; (3) simulation of gate oxide degradation during long-term circuit operation; (4) determination of overall circuit performance after hot-electron stress. For the modeling of the gate oxide degradation in nMOS transistor, a localized triangular charged density distribution function has been introduced in the drain end of the channel. This model was effective in explaining the local electric potential near the drain, especially on the flatband voltage and also the changes in the local channel electron mobility. To model the behavior of nMOS transistor with local oxide damages, a new one-dimensional I-V equation has been derived and implemented in a generic circuit simulator, iSMILE program. For the modeling of gate oxide degradation process, the rate equations governing the generation of interface states have been implemented for dynamic circuit operating conditions. With these mechanisms implemented, the iSMILE program has been able to simulate the degradation of circuit performances dynamically. For large scale reliability simulation, simpler models have been devised and used in the iDSIM2 program.

Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT techniques of Scan Path and Built in Test are described. An engineering methodology that uses the Genesil Silicon Compiler to produce a VLSI design, DFT-CHIP, which utilizes the DFT Scan Path technique is presented. Included are the procedures for using Genesil's simulation, timing analysis and automatic test generation features. The steps taken to fabricate the DFT-CHIP design through MOSIS are discussed. The methodology used to test the fabricated DFT- CHIP design on the Tektronix DAS 9100 tester is described. Appendix A and Appendix B provide copies of the Genesil check functions written for use during simulation on the DFT-CHIP design. Appendix C specifies the Genesil timing information for the DFT-CHIP design. Appendix D lists the conversion program which translates Genesil produced test vector files to the file format used during testing on the Tektronix tester.

The problem of VLSI design verification through circuit extraction was analyzed. The problems of creating a simple template format, the permutability of pins, maintaining connectivity, and performance were focused on. A generic template extractor (GENTEX) was developed in the C programming language for use as a testbed to find solutions to these problems. Six different extraction algorithms were tested with GENTEX and compared based on performance. EDIF translation programs were used to interface with GENTEX on both the input and output sides. One translation program converted an EDIF representation of a schematic into the template format used by GENTEX. The other translation program converted the output of GENTEX into a schematic in EDIF. The results of the performance analysis showed that an extraction algorithm based on searching the data structures by node rather than by component type provided the best performance. The results also showed that comparing the number of connections to a node within a template to the actual number of connections to a node within the circuit being extracted, not only eliminated any connectivity problems but also increased performance. VLSI, VLSI Verification, Circuit extraction, CAD Tools.

This report describes the use of the University of Washington/Northwest VLSI Consortium's package of VLSI design tools. The tools described are: Functional Design Tools; Layout Tools; Display tools; Rule Checkers; Circuit Extractor; Simulation Tools; and Utilities/Miscellaneous.

Part 1: Scalable CMOS design rules are developed for the MOSIS community to facilitate fabrication from a single design at 3 microns and 1.3 microns VHSIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technology are explored in this project. Three different CMOS PLA circuit styles are described: the large PLA uses a gated OR plane and is useful for a system with large number of inputs; the moderate PLA and the small PLA are ripple varieties with the former having the capability of handling a larger number of inputs than the latter. Path Programmable Logic (PPL), which is a folded form of a PLA, is also studied. A symbolic form of representation is developed and future PPL development activities are discussed. The PPL approach has a size and flexibility advantage over the other PLA approaches - except in applications requiring large PLA's.

Continuing work on thermal oxidation of silicon (at pressures to 20 atm) is discussed along with work on ion implantation (Boltzman transport modeling, range statistics, and record mechanisms). CVD and silicide technology, interface physics, and the continuing development of the STANFORD SUPREM process modeling program.

Continuing work on thermal oxidation of silicon (at pressures to 20 atm) is discussed along with work on ion implantation (Boltzman transport modeling, range statistics, and record mechanisms). CVD and silicide technology, interface physics, and the continuing development of the STANFORD SUPREM process modeling program.

This report discusses work completed toward the development of a user-oriented, multilevel simulation system for the VLSI circuit designer. Design representations which include several different levels of design have been developed. Two design aids, a mixed circuit and logic level simulator and timing abstraction aid for behavioral simulation have been developed. In addition, an interactive user-machine interface for these design aids has been developed. (Author)

During the period covered by the grant, two books and ten research papers were written under grant sponsorship. In addition nineteen of the research papers were written and published in conference proceeding. Ten other research manuscripts are now nearing completion. Titles of some of the completed work include: EIGNENVALUES AND EXPANDERS, A FRAMEWORK OF SOLVING VLSI GRAPH LAYOUT PROBLEMS, TIGHT BOUNDS ON THE COMPLEXITY OF PARALLEL SORTING, WAFER-SCALE INTERGRATION OF SYSTOLIC ARRAYS, and THE AVERAGE CASE ANALYSIS OF SOME ON-LINE ALGORITHMS FOR BIN PACKING.

We describe the design of the network design frame, (NDF), a self-timed routing chip for a message-passing concurrent computer. The NDF uses a partitioned data path, low-voltage output drivers, and a distributed token-passing arbiter to provide a bandwidth of 450Mbits/sec into the network. Wormhole routing and bidirectional virtual channels are used to provide low latency communications, less than micro seconds latency to deliver a 216 bit message across the diameter of a 1K node machine. To support concurrent software systems, the NDF provides two logical networks, one for user messages and one for system messages, that share the same set of physical wires. To facilitate the development of network nodes, the NDF is a design frame. The NDF circuitry is integrated into the pad frame of a chip leaving the center of the chip uncommitted.

In this paper we present a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to prove its performance. We show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. Our design of the 8 x 8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2 mu CMOS technology. In comparison to the existing designs, our approach offers many advantages that can be further explored for even higher performance.

This project has investigated novel design technologies for energy-efficient VLSI systems. Its primary focus has been on charge-recovery circuits. These circuits achieve higher energy efficiency than their conventional counterparts by steering currents to flow across devices with low voltage drops, while recycling undissipated energy in parasitic capacitors. Previous investigations into charge recovery have resulted in complex circuits and architectures that are impractical for high-speed design. This project has led to the discovery of practical low-complexity charge-recovery circuits which achieve high energy efficiency and achieve clock frequencies in excess of 1GHz. The results of this research have been validated through silicon prototyping and experimentation. For four of the inventions resulting from this project, the University of Michigan has filed utility and provisional patent applications with the US Patent and Trademark Office.

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.