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This is the supplemental disk to "VLSI Design and Hardware Description Languages", an advanced-undergraduate/graduate level introduction to VLSI chip design with the HDL Verilog, which includes full code listings for the book. The core project of this book is the implementation of a RISC-family/MIPS-ish processor, ready for tapeout to physical silicon. This book describes the methodology used to design and implement this processor, including co-simulation between a high-level interpreter model along with an HDL model, as well as processor testing on a physical chip.  The unpacked archive "1_TO_4.ZIP" contains the following sections. 1  VERILOG Examples This section contains the VERILOG examples of Chapter 11 of the book. It  supports computer aided searching and own simulations. 2  Interpreter Model This is the complete VERILOG model of the RISC processor TOOBSIE on the behavior  level. It serves as a reference for the instruction set. 3  Coarse Structure Model This is the complete VERILOG model of the RISC processor TOOBSIE on the register  transfer level and below. 4  Operating System and Examples The operating system VOS supports more comfortable experiments with the Coarse  Structure Model. For this purpose, there are also example application programs.  This section, however, does not belong to the actual target of the book.