VLSI Chip Design with the Hardware Description Language VERILOG - Info and Reading Options
An Introduction Based on a Large RISC Processor Design
By Ulrich Golze
"VLSI Chip Design with the Hardware Description Language VERILOG" is published by Springer in Aug 23, 2014 - Berlin, Heidelberg s.l and it has 374 pages.
“VLSI Chip Design with the Hardware Description Language VERILOG” Metadata:
- Title: ➤ VLSI Chip Design with the Hardware Description Language VERILOG
- Author: Ulrich Golze
- Number of Pages: 374
- Publisher: Springer
- Publish Date: Aug 23, 2014
- Publish Location: Berlin, Heidelberg s.l
“VLSI Chip Design with the Hardware Description Language VERILOG” Subjects and Themes:
- Subjects: ➤ Data processing - Design and construction - Computer-aided design - Verilog (Computer hardware description language) - RISC microprocessors - Very large scale integration - Integrated circuits - Integrated circuits, very large scale integration - Verilog (computer hardware description language) - Risc microprocessors
Edition Specifications:
- Format: paperback
Edition Identifiers:
- The Open Library ID: OL27957796M - OL13554483W
- ISBN-13: 9783642646508 - 9783642610011
- ISBN-10: 3642646506
- All ISBNs: 3642646506 - 9783642646508 - 9783642610011
AI-generated Review of “VLSI Chip Design with the Hardware Description Language VERILOG”:
"VLSI Chip Design with the Hardware Description Language VERILOG" Description:
Open Data:
This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC
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