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This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: ̲= tan-1(Q/I). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: ̲= tan-1(Q/I). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL simulation program.

In Deep Sub Micron (DSM) technologies, circuits fail to meet the timings estimated during synthesis after completion of the layout which is termed as âTiming Closureâ problem. This work focuses on the study of reasons for failure of timing closure for a given synthesis solution. It was found that this failure is due to non-adherence of synthesizerâs assumptions during placement. A synthesis aware new placer called ANUPLACE was developed which adheres to assumptions made during synthesis. The new algorithms developed are illustrated with an example. ANUPLACE was applied to a set of standard placement benchmark circuits. There was an average improvement of 53.7% in the Half-Perimeter-Wire-Lengths (HPWL) with an average area penalty of 12.6% of the placed circuits when compared to the results obtained by the existing placement algorithms reported in the literature.

Cyclic Spectrum Analysis exploits the cyclostationary properties of signals and systems. Military use of this technology is focused on its use in a near real time analytical environment. Such a system requires high speed arithmetic processing in calculating large Fourier transforms quickly. This thesis reviews a previous implementation and then presents a new design using Verilog hardware description language and the Epoch silicon compiler. Using these modern computer aided design tools, the ASIC design was simulated and layout completed using a one micron, two-metal process rule set. The final layout consists of 434,138 transistors on a 11,190 x 15,642 micron die. Simulations indicated that the chip would be capable of operating at a 25 Mhz clock rate while dissipating .8 watts of power. Embedded timing analysis tools displayed all critical timing paths which allowed the identification of specific design improvements. If implemented, these changes could double the clock rate of the processor.

Cyclic Spectrum Analysis exploits the cyclostationary properties of signals and systems. Military use of this technology is focused on its use in a near real time analytical environment. Such a system requires high speed arithmetic processing in calculating large Fourier transforms quickly. This thesis reviews a previous implementation and then presents a new design using Verilog hardware description language and the Epoch silicon compiler. Using these modern computer aided design tools, the ASIC design was simulated and layout completed using a one micron, two-metal process rule set. The final layout consists of 434,138 transistors on a 11,190 x 15,642 micron die. Simulations indicated that the chip would be capable of operating at a 25 Mhz clock rate while dissipating .8 watts of power. Embedded timing analysis tools displayed all critical timing paths which allowed the identification of specific design improvements. If implemented, these changes could double the clock rate of the processor.

This is the supplemental disk to "VLSI Design and Hardware Description Languages", an advanced-undergraduate/graduate level introduction to VLSI chip design with the HDL Verilog, which includes full code listings for the book. The core project of this book is the implementation of a RISC-family/MIPS-ish processor, ready for tapeout to physical silicon. This book describes the methodology used to design and implement this processor, including co-simulation between a high-level interpreter model along with an HDL model, as well as processor testing on a physical chip.  The unpacked archive "1_TO_4.ZIP" contains the following sections. 1  VERILOG Examples This section contains the VERILOG examples of Chapter 11 of the book. It  supports computer aided searching and own simulations. 2  Interpreter Model This is the complete VERILOG model of the RISC processor TOOBSIE on the behavior  level. It serves as a reference for the instruction set. 3  Coarse Structure Model This is the complete VERILOG model of the RISC processor TOOBSIE on the register  transfer level and below. 4  Operating System and Examples The operating system VOS supports more comfortable experiments with the Coarse  Structure Model. For this purpose, there are also example application programs.  This section, however, does not belong to the actual target of the book.

VLSI CAD systems are typically large and undergo frequent changes. A frustrating aspect of these changes is that so little of the old available programs can be reused. The reason is that it takes too much time and effort to find the reuseable pieces and recast them for the new use. We believe that such systems should be designed for reusability by anticipating change. Our thesis is that this goal can be achieved by designing the software as layers of problem oriented languages, which are implemented by suitably extending a base language. A language layer rarely needs to be adapted to changes, only the application (i.e. algorithm) needs to be changed. We illustrate this methodology with respect to VLSI CAD programs and a particular language layer: a language for handling networks. A concept shared by many CAD programs is that of networks consisting of components and their interconnects. We capture this common part by providing a language for handling network problems. Such a language consists of our base language (EC or Lisp) plus data types, operations and control structures that are relevant to network problems. The network language is but one of several languages used; other languages we use deal with sets, two dimensional layout structures, waveforms, etc. The discussion of the network language illustrates this technique. We present two different implementation of the above philosophy. The first uses UNIX and Enhanced C, a set oriented language supporting data abstraction based on C. The second approach uses Common Lisp on a Lisp machine. In each case, we describe the basic technique and its applications. We concluded by comparing the two approaches.

The construction of Fast Fourier Transform (FFT) processors is discussed. Pipeline and parallel-pipeline organizations are developed and are shown to meet the constraints imposed by VLSI. Various circuit technologies for the construction of these processors are compared, and the description of a set of NMOS chips are given. A technique for reducing the latency of the adders internal to the chips is also presented. Finally, a broad set of possible FFT organizations is discussed. (Author)

The construction of Fast Fourier Transform (FFT) processors is discussed. Pipeline and parallel-pipeline organizations are developed and are shown to meet the constraints imposed by VLSI. Various circuit technologies for the construction of these processors are compared, and the description of a set of NMOS chips are given. A technique for reducing the latency of the adders internal to the chips is also presented. Finally, a broad set of possible FFT organizations is discussed. (Author)

This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root. Keywords include: Very large scale integration (VLSI); and Floating point chip design.

In order to appreciate the critical hardware and software problems associated with the definition and design of very large scale integrated circuits or integrated systems including 10,000 - 1,000,000 transistors in a single silicon chip, incisive experiments conducted with actual operating chips are indispensible. The objective of this project is to establish, within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user-generated custom I.C. designs.

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

One of the new technique which is notable for dealing problems such as high frequency effect due to inductance and capacitance in physical layout level other than existing of techniques. For most designs for the use of 45nm processing technology the analysis using a static approach is no longer sufficient and it becomes mandatory to analyse the actual variation of the supply voltage with respect to time for detecting chip failure conditions.In this paper we deal with the IR drop analysis of the Diagonal power grid and orthogonal power grid, comparison between the diagonal and orthogonal power grid. Full chip Diagonal power grid static and dynamic IR drop analysis optimization of power  in vlsi digital design using red hawk for nanometer era.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems is an active peer-reviewed academic journal covering VLSI systems, wafer scale integration, multi-chip modules, mixed analog-digital systems, VLSI/ULSI neural networks and their applications, cost performance tradeoffs in VLSI/ULSI. It was established in 1993 and is published monthly by the Institute of Electrical and Electronics Engineers. This journal focuses on the research, development, and applications of VLSI systems, including integrated circuit design, fabrication, testing, and packaging, reviews, applications, and tutorials including novel VLSI/ULSI approaches. The journal features original research papers, review articles, and technical notes that contribute to the advancement of VLSI technology, covering a broad range of topics, including VLSI architecture, digital circuit design, analog and mixed-signal circuits, system-on-chip design, and low-power design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems can be found online at: www.ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=92 The ISSN is: 1063-8210

This report summarizes progress on VLSI (Very Large Scale Integration) Systems Research Projects from November 1981 to April 1983, inclusive. The major areas under investigation have included: analysis and synthesis design aids, applications of VLSI, special purpose chip design, VLSI computer architectures, signal processing algorithms and architectures, reliability studies, hardware specification and verification, VLSI theory, and VLSI fabrication. The major research problems are introduced and progress is discussed; the Appendix contains a list of published research papers from these projects. (Author)

In order to appreciate the critical hardware and software problems associated with the definition and design of very large scale integrated circuits or integrated systems including 1000 - 1,000,000 transistors in a single silicon chip, incisive experiments conducted with actual operating chips are indispensible. The objective of this project is to establish within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user-generated custom I. C. designs.

Dr.RASHID

Dr.RASHID

xii,546p

The VTST project developed a set of Built-In-Self-Test (BIST) methodologies and implemented them in the VTST Computer Aided Design (CAD) toolset. These test methodologies include a pseudo- exhaustive parallel BIST technique that utilizes an efficient test signal reduction method for combinational circuits based on Dr. Chen's research. This technique reduces the size of the test pattern generator (TPG) and the number of test patterns required for a given Circuit Under Test (CUT). Dr. Chen's method was extended to include methods for testing storage elements, i.e., sequential circuits. The VTST toolset includes a non-scan circular BIST method, full and partial-scan methodologies, and circular BIST combined with pseudo-partial scan. Programs are included for fault simulation, partitioning circuits into subcircuits to improve fault coverage, removing redundant faults, synthesizing BIST circuits, and automatically inserting the BIST circuits into the original circuit. The VTST toolset interfaces with LSI Logic's CMDE CAD toolset, generating BlST'ed circuits in LSI's NDL format. A VHDL parser is included that allows VHDL designs to be input to VTST; VHDL output can also be generated. The tools are hosted on a Sun workstation and permit concurrent engineering use on multiple machines. Several test circuits were processed to verify correct operation.

In order to appreciate the critical hardware and software problems associated with the definition and design of very large scale integrated circuits or integrated systems including 1000 - 1,000,000 transistors in a single silicon chip, incisive experiments conducted with actual operating chips are indispensible. The objective of this project is to establish within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user-generated custom I. C. designs.

In order to appreciate the critical hardware and software problems associated with the definition and design of very large scale integrated circuits or integrated systems including 10,000 - 1,000,000 transistors in a single silicon chip, incisive experiments conducted with actual operating chips are indispensible. The objective of this project is to establish, within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user-generated custom I.C. designs.

ADA146328

This item represents a case in PACER, the U.S. Government's website for federal case data. If you wish to see the entire case, please consult PACER directly.

33 p. 28 cm

Trimester 2 - 2018/2019

Trimester 2 - 2018/2019

Trimester 2 - 2018/2019

viii, 239 p. : 25 cm

Neural networks tend to fall into two general categories: (1) software simulations, or (2) custom hardware that must be trained. The scope of this project is the merger of these two classifications into a system whereby a software model of a network is trained to perform a specific task and the results used to synthesize a standard cell realization of the network using automated tools.

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

VLSI Design

VLSI Design

In this paper, we propose algorithms and software for parallel implementation of conversion of VLSI Layout Data from CAD format Gerber and MEBES into an internal representation and then into format of automatic mask inspection system T29. The software is developed on basis of OpenMP technology to work on PC with 4-core processor. It is shown that using parallel computing speeds up a conversion process. In the future we are planning to develop similar tools for data conversion from CIF and DFX formats into the internal format, and further into format GDS-II. These tools allow developing a program complex of topological data processing to work with automatic mask inspection system made by R&D Company “KBTEM-OMO” of “Planar” Corporatio

Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described. Applications to communications circuits are presented.

A novel two-dimensional parallel computing method for real-time Kalman filtering is presented. The mathematical formulation of a Kalman filter algorithm is rearranged to be the type of Faddeev algorithm for generalizing signal processing. The data flow mapping from the Faddeev algorithm to a two-dimensional concurrent computing structure is developed. The architecture of the resulting processor cells is regular, simple, expandable, and therefore naturally suitable for VLSI chip implementation. The computing methodology and the two-dimensional systolic arrays are useful for Kalman filter applications as well as other matrix/vector based algebraic computations.

A software simulation of long constraint length Viterbi decoders was developed. This software closely follows the hardware architecture that was chosen for the Very Large Scale Integration implementation. The program is used to validate the design of the decoder and to generate test vectors for the VLSI circuits.

A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

see report With chip size reaching one million transistors. the complexity of VLSI algorithms -i.e., algorithms implemented as digital VLSI circuits is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm. we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design. because the timing properties of a circuit are essential not only to its real-time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason. delay-insensitive techniques are particularly attractive for VLSI synthesis. A circuit is delay-insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite [17]. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: The class of entirely delay insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises about delay-insensitivity. Speed-independent techniques assume that delays in gates are arbitrary, but that there are no delays in wires.

Presented is the initial step for the eventual implementation of a programmable GIC switched capacitor filter in a GaAs process. This thesis is the initial engineering effort in the accomplishment of this goal. The focus of this thesis is to design, fabricate, and test all necessary components for the construction of a GIC switched capacitor filter. All components will be stand alone so that future testing of each component may be accomplished. VLSI implementation will be accomplished using the Magic Cad package and the Vitesse HGaAs3 fabrication process. The simulation of the components will be accomplished using HSpice.

This report summarizes progress in the DARPA funded projects in the areas of multiprocessor architecture and software, and computer-aided design from April 1987 to October 1987. The major areas under investigation have included: analysis and synthesis design aids, high performance chip design, multiprocessor and VLSI computer architectures. The major research problems are introduced and progress is discussed; the Appendix contains a list of published research papers from these projects. Keywords: VLSI, Design automation, Computer aided design, Special purpose chips, VLSI computer architecture, Routing, Layout, Memory reliability.

Tapered, coupled, microstrip transmission lines are an increasingly important part of high-speed digital circuits. These lines, used as interconnects between integrated circuit devices, are modeled using and iteration-perturbation approach applied in the spatial domain. The approach is used first to solve the static problem, and then to iterate on the static solution to obtain the charge and current distributions on the lines at different frequencies. From this model, a frequency-dependent scattering parameter characterization is determined. Results for typical geometries are presented and are compared with those published by other authors. A time-domain simulation of pulse propagation through the tapered, coupled, microstrip lines is performed. The frequency-domain scattering parameters are inverse Fourier transformed to obtain the time-domain Green's function. The input pulse is convolved with the Green's function, and a Newton-Raphson algorithm is applied to account for nonlinear loads. Good agreement is found with other published results. Finally, some experimental results are shown and an equivalent circuit is proposed. The experimental results verify the model, while the equivalent circuit allows the time-domain simulation to be performed in less time with a negligible loss in accuracy. Results show that the equivalent circuit gives essentially the same time-domain response in about one-tenth of the simulation time. Theses.

Feasibility demonstration of a trace-level water vapor sensor has been performed in Phase 1. The sensor is critically needed in semiconductor industry, where trace concentrations of water in highly reactive gases used in Very Large Scale Integration (VLSI) manufacturing decrease significantly the yield of IC chips produced. The sensor described is based on optical spectroscopy in the middle infrared region, and uses a novel laser source, based on nonlinear frequency conversion. In Phase 1 we have demonstrated both the feasibility of producing such a source (diode laser-pumped, room-temperature operation), and the feasibility of its application for sensitive frequency-modulation spectroscopy of water vapor in the middle infrared region. The results achieved open up the potential to develop a novel optical microsensor capable of reaching the required ultra-high detection sensitivity in a package suitable for use in industrial environments.

With chip size reaching one million transistors. the complexity of VLSI algorithms-i.e., algorithms implemented as a digital VLSI circuit-is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm, we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically-into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design, because the timing properties of a circuit are essential not only to its real time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason, delay. insensitive' techniques are particularly attractive for VLSI synthesis. A circuit is delay-insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: It has been proved in that the class of entirely delay-insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises to delay-insensitivity.

There are eleven Georgia Tech VLSI designs in the AHAT Program. Each of these designs has been produced by Georgia Tech using the Genesil Silicon Compiler. Each design has passed the design verification process at Silicon Compiler Systems/Mentor Graphics and each has been fabricated in a bulk CMOS process (fabrication of certain chips was not complete when this document was released). Each of the Georgia Tech designs listed in Table 1 is being delivered to USASDC and to the Harris Corporation for conversion and fabrication in a rad-hard process. The program under which this work is done is AHAT (Advanced Hardened Avionics Technology). This document includes design information for the Georgia Tech eight point crossbar switch chip, GT-VSM8.

The main objective of the Lincoln Restructurable VLSI Program (RVLSI) is to develop methodologies and architectures for implementing wafer-scale systems with complexities approaching a million gates. In our approach, we envisage a modular style of architecture comprising an array of cells embedded in a regular interconnection matrix. Ideally, the cells should consist of only a few basic types. The interconnection matrix is a fixed pattern of metal lines augmented by a complement of programmable switches or links. Conceptually, the links could be either volatile or nonvolatile. They could be of an electronic nature such as a transistor switch, or could be permanently programmed through some mechanism such as a laser. The RVLSI Program is currently focusing on laser-formed interconnect. The link concept offers the potential for a highly flexible, restructurable type of interconnect technology that could be exploited in a variety of ways. For example, logical cells or subsystems found to be faulty at wafer-probe time could be permanently excised from the rest of the wafer. The flexible interconnect could also be used to 'jump around' faulty logic and tie in redundant cells judiciously scattered around the wafer for this purpose.