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An analysis of the MacPitts silicon compiler is presented. The emphasis of the analysis is on the interrelationshp between algorithmic syntax and resulting circuit structure. Errors inherent to the silicon compiler are investigated, and corrections to the errors are proposed. (Author)

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

The concept and application of silicon compilers is described. The process of employing the MacPitts silicon compiler to design an 8-bit pipelined digital multiplier is presented, and the resulting design is evaluated. The process of installing and debugging the MacPitts compiler and the Caesar VLSI graphics editor on the VAX 11/780 computing facilities at NPS is documented in appendices. (Author)

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

The light sensitivity of p-n junctions in silicon integrated circuits has been investigated and the spectral and temporal response of several structures in an integrated circuit measured. A model for the spectral response was developed based on models previously used to study solar cell response. This model takes into account the depth and the active area of the carrier collecting junction and demonstrates the shifting of the peak spectral response towards shorter wavelengths as junction depth and active area decreases. Measurements of the spectral response of junctions in an integrated circuit were compared with the predicted responses. An investigation into the temporal response of p-n photodiodes has shown that the response time of the diode is dependent on both the geometry of the junction and the wavelength of light generating the carriers. Response times for structures in the integrated circuit were measured using a He-Ne laser operating at 0.632 micron. Keywords include: Integrated optoelectronics; Integrated photodetectors; Optical interconnects; Optical testing; and Laser testing.

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Silicon contact for area reduction of integrated circuits

The purpose of this research effort was to investigate the feasibility of applying the silicon micromachining technique to thermal management as applied to integrated circuits and wafer scale integration techniques. Three silicon micromachined structures and an untextured reference wafer were compared as heat-dissipating surfaces. These four surfaces were realized using 3-inch diameter, single crystal silicon wafers. The following structures were micromachined in silicon wafers using wet chemical, anisotropic etching and photolithographic techniques: (1) randomly spaced and sized pyramids in (100)-oriented silicon, (2) deep vertical-wall grooves in (110)-oriented silicon, and (3) micro-fluid channels in (100)-oriented silicon. The heat- dissipating silicon wafers were epoxied to silicon wafers hosting heat-producing devices to realize a silicon wafer thermal module, simulating the wafer scale integration packaging technique. Two types of heat-producing devices were compared: (1) n-diffused integrated circuit die resistors, and (2) thin-film aluminum resistors. Two configurations of the integrated circuit die were also compared: (1) a single, centered, integrated circuit die and (2) four, centered, integrated circuit die.

This progress report summarizes achievements in Dr. Adibi's research group at Georgia Institute of Technology in the area of All-Optical Photonic Integrated Circuits in Silicon, supported by Air Force Office of Scientific research (AFOSR) PECASE award since December 2005. Only major achievements with very brief description are listed in this report. Detailed information can be found in the recent publications or can be directly requested from Dr. Adibi. This AFOSR-supported research was started in December 2005 and is directed toward exploiting and enhancing the linear and nonlinear optical properties of silicon micro/nano cavities for chip-scale sensing and signal processing. To achieve this goal, in what follows, different steps (including theoretical and modeling tools development, microcavity fabrication and characterization techniques, and methods to develop chip-scale devices) to realize this chip-scale signal processing will be discussed. Our research in this field has already resulted in a number of scientific publications and technical presentations. A complete list of journal papers and conference presentations is included at the end of this report. AFOSR support has been acknowledged in all these publications and presentations.

The effort funded by this contract encompassed two principal objectives: First, the creation of a silicon carbide device prototyping capability at Mississippi State University by the creation of the first SiC fab line independent of commercial control. Secondly, the demonstration of a power Schottky barrier diode (SBD) prototyped in preproduction lot size. This final report documents the detailed description of the design, fabrication methodology, and testing results of the 15,000 SBD's fabricated and tested. The principle accomplishments of the funded effort are: The completion of a SiC foundry including fabrication services. Schottky barrier diodes were fabricated with reverse blocking characteristics averaging 500 volts, and with on-state forward voltage drops of 2.5 volts at 100 amps/cm2. Finally, a commercial supplier of advanced and specialty discrete power devices evaluated and subsequently used the SBD's developed under this program to announce and release the first-ever commercial SiC power device using their proprietary high-power-density packaging, thus fulfilling the initial promise of the prototype manufacturing facility.

Mow to integrate optoelectonic devices with Si ICs is the key to the success of the optical interconnect technology. The substrate removal technique uses mechanical polishing and wet chemical etching to remove the substrate. After removal of the substrate, metal layers are deposited on the backside of the wafer and the VCSEL devices are ready to be mounted onto SI chips. The removal of the substrate enables the flip-chip bonding for 850 run VCSELs and reduces the height of the defices.

Fabrication method produces stable and reliable metallic systems for interconnections, contact pads, and bonded leads in silicon planar integrated circuits. The method is based on substrate isolation of the interconnection metal from the contact pad and bonded wire.

Fabrication method produces stable and reliable metallic systems for interconnections, contact pads, and bonded leads in silicon planar integrated circuits. The method is based on substrate isolation of the interconnection metal from the contact pad and bonded wire.

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

The architecture and structures used by the MacPitts silicon compiler to design integrated circuits are described, and the capabilities and limitations of the compiler are discussed. The performance of several combinational and pipeline adders designed by MacPitts and a hand-crafted pipeline adder are compared. Several different MacPitts design errors are documented. Tutorial material is presented to aid in using the MacPitts interpreter and to illustrate timing analysis of MacPitts-designed circuits using the program Crystal.

The architecture and structures used by the MacPitts silicon compiler to design integrated circuits are described, and the capabilities and limitations of the compiler are discussed. The performance of several combinational and pipeline adders designed by MacPitts and a hand-crafted pipeline adder are compared. Several different MacPitts design errors are documented. Tutorial material is presented to aid in using the MacPitts interpreter and to illustrate timing analysis of MacPitts-designed circuits using the program Crystal.

Available from National Technical Information Service, Springfield, Va

Available from National Technical Information Service, Springfield, Va

This program focuses on Field-Hardness ; specifically, the parasitic N-channel leakages which can result on the edge of an N-Channel transistor from source to drain, from drain of one device to the drain of another or from drain (across the CMOS P-well) to the N-substrate (Vdd). This type of leakage normally causes device failure well before the more publicized gage-oxide problem cause Vt to drift out of spec. By butting a poly field-plate directly next to the device in the width direction (for example) we dramatically minimize the positive charge which can build up during irradiation since there is a minimal amount of oxide under this field plate; this technique is used to extend previously used concepts of using buried P+ guard-rings and special gate/field overlap layout to improve the Radiation Hardness of Integrated Circuits and has the added bonus of obviously not being sensitive to Carrier Freeze-out phenomena which degrades P+ guard-ring usefulness at a cryogenic temperatures.

We have demonstrated the first three dimensional integration of a high quality compound semiconductor infrared imaging detector array directly on top of a foundry-produced silicon neuromorphic image processing circuit. There is great potential for this new technology in neuromorphic image processing applications. This new ability to construct complex locally connected neuromorphic focal-plane processors with direct massively parallel connections to high quality compound semiconductor imaging arrays will lead to new levels of sophistication in focal-plane processing. During this research, thin film p-i-n and metal-semiconductor-metal (MSM) detectors were fabricated and tested. A four-by-four array of detectors was integrated onto a metallized silicon substrate and directly on top of an array of silicon circuits. The yield of each of these arrays was 100%, i.e., every detector was functional, and, in the integration onto silicon circuitry, every circuit underneath the detectors was also functional.

The architecture and structures used by the MacPitts silicon compiler to design integrated circuits are described, and the capabilities and limitations of the compiler are discussed. The performance of several combinational and pipeline adders designed by MacPitts and a hand-crafted pipeline adder are compared. Several different MacPitts design errors are documented. Tutorial material is presented to aid in using the MacPitts interpreter and to illustrate timing analysis of MacPitts-designed circuits using the program Crystal. Keywords include: VLSI Design; MacPitts silicon compiler; Pipeline adder; Block carry look ahead addition; Data-Path; and Weinberger Array.

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

We present an accurate and fast 3D simulation scheme for out-of-plane grating couplers, based on two dimensional rigorous (finite difference time domain) grating simulations, the effective index method (EIM), and the Rayleigh-Sommerfeld diffraction formula. In comparison with full 3D FDTD simulations, the rms difference in electric field is below 5% and the difference in power flux is below 3%. A grating coupler for coupling from a silicon-on-insulator photonic integrated circuit to an optical fiber positioned 0.1 mm above the circuit is designed as example.

Walker is a pioneer in the Silicon Valley hightech industry. SILICON DESTINY is the history of integrated circuits optimized for a specific customer or application. It is an oral history, told in the words of the technologists who invented the concepts. It also emphasizes the financial aspects of starting new companies & eventually taking them public. It will be of interest to electrical engineers & venture capitalists. To order, contact C.M.C. Publications, 565 Sinclair Road, Milpitas, CA 95035. To order by phone in the U.S., call 8005456698. Outside the U.S., you may order by calling 408 9451557; there is a $5 addon for orders outside the United States. Or you may order through FAX at 408 9451135. VISA & MasterCard are welcome.