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The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

High-performance MOS circuits are frequently designed using pre- charged and dynamic logic. This requires the use of multiple phases of the system clock to ensure that the circuitry is pre-charged and refreshed at the proper times during each clock cycle. Finite-state machines used to control this type of logic must therefore be constructed as multi-phase sequential logic with inputs and outputs stable during the appropriate phases. The timing optimization of multi-phase logic entails the reduction of the overall cycle time of the machine as well as input to output delays by distributing computation throughout the entire clock cycle. Currently, no tools are available to automatically perform this optimization task for multi-phase logic. We have developed such a tool as a set of extensions to the combinational logic optimization tool, misII. Our algorithms yield improvements that are 20% better than what is achievable using only combinational logic optimization tools that do not move logic across latches. Furthermore, we achieve 65% of the improvements possible in the circuits show average input to output delay improvements of almost 20% with area penalties of less than 12%. For a four-phase controller used in the SPUR processor it yields an improvement in cycle time of 21% with an area penalty of 21%.

Motivated by rapidly advancing capabilities for extensive nanoscale patterning of optical materials, I propose an approach to implementing photonic sequential logic that exploits circuit-scale phase coherence for efficient realizations of fundamental components such as a NAND-gate-with-fanout and a bistable latch. Kerr-nonlinear optical resonators are utilized in combination with interference effects to drive the binary logic. Quantum-optical input-output models are characterized numerically using design parameters that yield attojoule-scale energy separation between the latch states.

The goals of the Wisconsin-English-Language-Arts Curriculum Project were (1) to study what should be taught in English language arts in grades K-12, (2) to develop a sequential curriculum for those grades, (3) to design, identify, and test appropriate teaching methods and instructional materials, and (4) to establish demonstration centers to determine the success of the curriculum recommendations. The sequential curriculum--eventually published as one volume, "English Language-Arts in Wisconsin" (ED 018 410)--was developed in three stages: literature and reading; speaking and writing; and language and grammar. Development of each stage involved committee discussions and reports, conferences, guest lecturers, and summer workshops. (Appendices of this report list participants in the project and provide a chronological account of the 5 years of the project's existence.) (JS)

Biometrics technologies have grown considerably in recent years with better computing and an expanding realm in which these tools are deployed. Among these, iris recognition demonstrates superior performance as a biometric, perhaps far exceeding the standard fingerprint recognition of past decades. Unfortunately, iris recognition is very computationally intensive, requiring near state-of-the-art traditional processing methods. Because of the complexity of iris recognition systems, many portable iris scanners are bulky, cumbersome and very expensive, often requiring laptop computers to carry out the computations. This is due to a reliance on sequential processing, the manner of computing we see in a typical personal computer. However, there is an alternative with parallel processing using multicore processors, field-programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). These devices can speed algorithms through parallel processing. Taking the algorithm developed by Dr. Robert Ives et al. of the United States Naval Academy for iris recognition, parallelizable parts of the algorithm can be translated for parallel processing. A parallel version of the algorithm may be substantially faster and physically much smaller implemented. This implementation is placed into an FPGA system in order to evaluate the performance of specific parts of the algorithm converted from sequential C code to parallel hardware logic with respect to speed and hardware footprint. Additionally, this project seeks to evaluate the feasibility of an entirely embedded iris recognition system comprised of both sequential C software and parallel hardware on a single chip and a discrete memory module. The resulting hardware is shown to be between 10 and 1000 times faster than current methods while being entirely embedded and independent of a host system for processing.

Biometrics technologies have grown considerably in recent years with better computing and an expanding realm in which these tools are deployed. Among these, iris recognition demonstrates superior performance as a biometric, perhaps far exceeding the standard fingerprint recognition of past decades. Unfortunately, iris recognition is very computationally intensive, requiring near state-of-the-art traditional processing methods. Because of the complexity of iris recognition systems, many portable iris scanners are bulky, cumbersome and very expensive, often requiring laptop computers to carry out the computations. This is due to a reliance on sequential processing, the manner of computing we see in a typical personal computer. However, there is an alternative with parallel processing using multicore processors, field-programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). These devices can speed algorithms through parallel processing. Taking the algorithm developed by Dr. Robert Ives et al. of the United States Naval Academy for iris recognition, parallelizable parts of the algorithm can be translated for parallel processing. A parallel version of the algorithm may be substantially faster and physically much smaller implemented. This implementation is placed into an FPGA system in order to evaluate the performance of specific parts of the algorithm converted from sequential C code to parallel hardware logic with respect to speed and hardware footprint. Additionally, this project seeks to evaluate the feasibility of an entirely embedded iris recognition system comprised of both sequential C software and parallel hardware on a single chip and a discrete memory module. The resulting hardware is shown to be between 10 and 1000 times faster than current methods while being entirely embedded and independent of a host system for processing.

The ability to learn and respond to recurrent events depends on the capacity to remember transient biological signals received in the past. Moreover, it may be desirable to remember or ignore these transient signals conditioned upon other signals that are active at specific points in time or in unique environments. Here, we propose a simple genetic circuit in bacteria that is capable of conditionally memorizing a signal in the form of a transcription factor concentration. The circuit behaves similarly to a "data latch" in an electronic circuit, i.e. it reads and stores an input signal only when conditioned to do so by a "read command". Our circuit is of the same size as the well-known genetic toggle switch (an unconditional latch) which consists of two mutually repressing genes, but is complemented with a "regulatory front end" involving protein heterodimerization as a simple way to implement conditional control. Deterministic and stochastic analysis of the circuit dynamics indicate that an experimental implementation is feasible based on well-characterized genes and proteins. It is not known, to which extent molecular networks are able to conditionally store information in natural contexts for bacteria. However, our results suggest that such sequential logic elements may be readily implemented by cells through the combination of existing protein-protein interactions and simple transcriptional regulation.

The ability to learn and respond to recurrent events depends on the capacity to remember transient biological signals received in the past. Moreover, it may be desirable to remember or ignore these transient signals conditioned upon other signals that are active at specific points in time or in unique environments. Here, we propose a simple genetic circuit in bacteria that is capable of conditionally memorizing a signal in the form of a transcription factor concentration. The circuit behaves similarly to a "data latch" in an electronic circuit, i.e. it reads and stores an input signal only when conditioned to do so by a "read command". Our circuit is of the same size as the well-known genetic toggle switch (an unconditional latch) which consists of two mutually repressing genes, but is complemented with a "regulatory front end" involving protein heterodimerization as a simple way to implement conditional control. Deterministic and stochastic analysis of the circuit dynamics indicate that an experimental implementation is feasible based on well-characterized genes and proteins. It is not known, to which extent molecular networks are able to conditionally store information in natural contexts for bacteria. However, our results suggest that such sequential logic elements may be readily implemented by cells through the combination of existing protein-protein interactions and simple transcriptional regulation.

In the past few years it has been shown that universal quantum computation can be obtained by projective measurements alone, with no need for unitary gates. This suggests that the underlying logic of quantum computing may be an algebra of sequences of quantum measurements rather than an algebra of products of unitary operators. Such a Sequential Quantum Logic (SQL) was developed in the late 70's and has more recently been applied to the consistent histories framework of quantum mechanics as a possible route to the theory of quantum gravity. In this letter, I give a method for deciding the truth of a proposition in SQL with nonzero probability of success on a quantum computer.

In the past few years it has been shown that universal quantum computation can be obtained by projective measurements alone, with no need for unitary gates. This suggests that the underlying logic of quantum computing may be an algebra of sequences of quantum measurements rather than an algebra of products of unitary operators. Such a Sequential Quantum Logic (SQL) was developed in the late 70's and has more recently been applied to the consistent histories framework of quantum mechanics as a possible route to the theory of quantum gravity. In this letter, I give a method for deciding the truth of a proposition in SQL with nonzero probability of success on a quantum computer.

Computability logic (CL) (see http://www.cis.upenn.edu/~giorgi/cl.html) is a semantical platform and research program for redeveloping logic as a formal theory of computability, as opposed to the formal theory of truth which it has more traditionally been. Formulas in CL stand for (interactive) computational problems, understood as games between a machine and its environment; logical operators represent operations on such entities; and "truth" is understood as existence of an effective solution, i.e., of an algorithmic winning strategy. The formalism of CL is open-ended, and may undergo series of extensions as the study of the subject advances. The main groups of operators on which CL has been focused so far are the parallel, choice, branching, and blind operators. The present paper introduces a new important group of operators, called sequential. The latter come in the form of sequential conjunction and disjunction, sequential quantifiers, and sequential recurrences. As the name may suggest, the algorithmic intuitions associated with this group are those of sequential computations, as opposed to the intuitions of parallel computations associated with the parallel group of operations: playing a sequential combination of games means playing its components in a sequential fashion, one after one. The main technical result of the present paper is a sound and complete axiomatization of the propositional fragment of computability logic whose vocabulary, together with negation, includes all three -- parallel, choice and sequential -- sorts of conjunction and disjunction. An extension of this result to the first-order level is also outlined.

This paper presents approaches to multi-level sequential logic synthesis-algorithms and techniques for the area and performance optimization of interconnected finite state machine descriptions. Interacting finite state machines are common in industrial chip designs. While optimization techniques for single finite state machines are relatively well developed, the problem of optimization across latch boundaries has received much less attention. Techniques to optimize pipelined combinational logic so as to improve area/ throughput have been proposed. However, logic cannot be straightforwardly migrated across latch boundaries when the basic blocks are sequential rather than combinational circuits. We present new techniques for the exploitation of sequential don't cares in arbitrary, interconnected sequential machine structures. Exploiting these don't care sequences can result in significant improvements in area and performance. We address the problem of migrating logic across state machine boundaries so as to make particular machines less complex at the possible expense of making others more complex. This can be useful from both an area and performance point of view. We present new optimization algorithms that incrementally modify state machine structures across latch boundaries. We discuss the use of more global state machine decomposition and factorization algorithms for area optimization. Finally, we present experimental results using these algorithms on sequential circuits.

The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions. In this paper, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of anon-scan sequential machine. The sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine. We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines.

It is well known that optimal logic synthesis can ensure fully testable combinational logic design. In this paper we show that optimal sequential logic synthesis can produce irredundant, fully testable finite state machines. Test generation algorithms can be used to remove all the redundancies in sequential machines resulting in a fully testable design. However, this method may require exorbitant amounts of CPU time. The optimal synthesis procedure presented in this paper represents a more efficient approach to achieve 100% testability. Synthesizing a sequential circuit from a State Transition Graph description involves the steps of state minimization, state assignment and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignment and logic optimization. In this paper we show that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. Unlike previous synthesis approaches to ensuring fully testable machines, there is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable.

Bell System Technical Journal, 60: 9. November 1981 pp 2259-2271. A Fault-Collapsing Analysis in Sequential Logic Networks. (Chang, S.J.; Breuer, M.A.)

By using the memristor's memory to both store a bit and perform an operation with a second input bit, simple Boolean logic gates have been built with a single memristor. The operation makes use of the interaction of current spikes (occasionally called current transients) found in both memristors and other devices. The sequential time-based logic methodology allows two logical input bits to be used on a one-port by sending the bits separated in time. The resulting logic gate is faster than one relying on memristor's state switching, low power and requires only one memristor. We experimentally demonstrate working OR and XOR gates made with a single flexible Titanium dioxide sol-gel memristor.

Bell System Technical Journal, 39: 2. March 1960 pp 295-332. Integrated Magnetic Circuits for Synchronous Sequential Logic Machines. (Gianola, U.F.)

Bell System Technical Journal, 39: 2. March 1960 pp 295-332. Integrated Magnetic Circuits for Synchronous Sequential Logic Machines. (Gianola, U.F.)

This report describes the test techniques for radiation characterizing medium and large-scale integration (MSI/LSI) sequential logic circuits where few internal nodes are available for testing. Four sequential logic devices, two transistor-transistor-logic (TTL) technology devices and two complementary-metal-oxide-silicon (CMOS) technology devices were characterized. The devices were characterized for gamma dose-rate logic upset, total gamma dose survivability, and neutron fluence survivability. The data has been analyzed to determine the applicability of the testing techniques and procedures. (Author)

Vadim Vasyukevich - Asynchronous Operators of Sequential Logic_ Venjunction _ Sequention

This article is from BMC Systems Biology , volume 8 . Abstract Background: Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results: This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions: A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

This article is from BMC Systems Biology , volume 8 . Abstract Background: Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results: This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions: A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

This volume was digitized and made accessible online due to deterioration of the original print copy.

This volume was digitized and made accessible online due to deterioration of the original print copy.

This volume was digitized and made accessible online due to deterioration of the original print copy.