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Being one of the most elegant sensory organs of the human body, anomalies in the retina can have serious consequences on the vision system and are indicative of specific medical conditions. Off the shelf fundus cameras are capable of acquiring high quality retinal images, yet accurate interpretation of retinal images remains a major bottleneck in the early detection of asymptomatic retinal conditions. Decades of research has led to numerous retinal image segmentation algorithms which can map blood vessels in retina images, and identify some of the most telling retina lesions. Despite this significant progress, how to derive personalized optimal parameters for automated mapping remains an open issue. In this talk, I will discuss our recent work in personalized modeling of blood vessel mapping algorithms. The technique is based on statistical fitting of selective image features to a statistical distribution, using a Sobel (or similar) edge detector as a “probe” to measure the personalized optimal threshold parameter for BV mapping. The approach allows systematic tradeoff analysis between detection sensitivity and false detection rates. The implementation of these mapping algorithms on a Pico FPGA card on a laptop achieves 30x acceleration over a CPU based implementation. We plan to utilize the very high level of parallelism offered by FPGA cluster/FPGA cards to extract region-based features for cloud-level image indexing/retrieval applications, and client crowd-based image feature processing and aggregation. ©2011 Microsoft Corporation. All rights reserved.

During this period, the eight investigators produced 10 papers with titles including Reliability in cellular arrays through data sharing, Interactive software systems for computer vision, On mapping homogeneous graphs on a linear array processor model, A parallel method for natural texture synthesis, and Embedding of networks of processors into hypercubes. (Author)

A new algorithm for the multiprocessor computation of the multidimensional discrete Fourier transform is presented. The algorithm eliminates the need for interprocessor communication and is highly scalable. The cost of eliminating interprocessor communication by this method is that one addition must be performed at each processing element for every input loaded into the machine. The algorithm is based on a new multidimensional discrete Fourier transform algorithm that computes a d-dimensional discrete Fourier transform by a set of independent k-dimensional discrete Fourier transforms (kd); it is a reduction algorithm in the sense that it has lowered the dimension of the Fourier transforms that are computed. The k-dimensional discrete Fourier transforms are performed on data derived from the input using only additions, and produce k-dimensional hyperplanes of the output array. Multidimensional discrete fourier transform algorithms, Parallel algorithms.

A new algorithm for the multiprocessor computation of the multidimensional discrete Fourier transform is presented. The algorithm eliminates the need for interprocessor communication and is highly scalable. The cost of eliminating interprocessor communication by this method is that one addition must be performed at each processing element for every input loaded into the machine. The algorithm is based on a new multidimensional discrete Fourier transform algorithm that computes a d-dimensional discrete Fourier transform by a set of independent k-dimensional discrete Fourier transforms (kd); it is a reduction algorithm in the sense that it has lowered the dimension of the Fourier transforms that are computed. The k-dimensional discrete Fourier transforms are performed on data derived from the input using only additions, and produce k-dimensional hyperplanes of the output array. Multidimensional discrete fourier transform algorithms, Parallel algorithms.

A new algorithm for the multiprocessor computation of the multidimensional discrete Fourier transform is presented. The algorithm eliminates the need for interprocessor communication and is highly scalable. The cost of eliminating interprocessor communication by this method is that one addition must be performed at each processing element for every input loaded into the machine. The algorithm is based on a new multidimensional discrete Fourier transform algorithm that computes a d-dimensional discrete Fourier transform by a set of independent k-dimensional discrete Fourier transforms (kd); it is a reduction algorithm in the sense that it has lowered the dimension of the Fourier transforms that are computed. The k-dimensional discrete Fourier transforms are performed on data derived from the input using only additions, and produce k-dimensional hyperplanes of the output array. Multidimensional discrete fourier transform algorithms, Parallel algorithms.

A new algorithm for the multiprocessor computation of the multidimensional discrete Fourier transform is presented. The algorithm eliminates the need for interprocessor communication and is highly scalable. The cost of eliminating interprocessor communication by this method is that one addition must be performed at each processing element for every input loaded into the machine. The algorithm is based on a new multidimensional discrete Fourier transform algorithm that computes a d-dimensional discrete Fourier transform by a set of independent k-dimensional discrete Fourier transforms (kd); it is a reduction algorithm in the sense that it has lowered the dimension of the Fourier transforms that are computed. The k-dimensional discrete Fourier transforms are performed on data derived from the input using only additions, and produce k-dimensional hyperplanes of the output array. Multidimensional discrete fourier transform algorithms, Parallel algorithms.

Parallel processing was motivated by the need to solve very large computational problems, such as the numerical solutions of partial differential equations in the context of computational fluid dynamics, structural mechanics, image processing, etc. This report surveys recent literature on parallel processing algorithms for mainly rings, meshes, and hypercubes. These algorithms include vector, matrix computations, fixed point iterations and linear equation solvers. A group property of above topologies has also been explored in an attempt to develop tools for algorithms and performance analysis. Some special sparsity structure of the iteration dependencies has also been examined. A necessary and sufficient condition for the reducibility of a dependency matrix with sparse, nonzero extended diagonals has been derived. Keywords: Communications traffic, Traffic distributions.

An explicit flow solver, applicable to the hierarchy of model equations ranging from Euler to full Navier-Stokes, is combined with several techniques designed to reduce computational expense. The computational domain consists of local grid refinements embedded in a global coarse mesh, where the locations of these refinements are defined by the physics of the flow. Flow characteristics are also used to determine which set of model equations is appropriate for solution in each region, thereby reducing not only the number of grid points at which the solution must be obtained, but also the computational effort required to get that solution. Acceleration to steady-state is achieved by applying multigrid on each of the subgrids, regardless of the particular model equations being solved. Since each of these components is explicit, advantage can readily be taken of the vector- and parallel-processing capabilities of machines such as the Cray X-MP and Cray-2.

The purpose of this study was to evaluate the parallel processing impact of MIMD (Multiple-Instruction Multiple-Data Path) computers on Flight Simulation Software. Basic mathematical functions and arithmetic expressions from typical Flight Simulation Software were selected and run on a MIMD computer to evaluate the improvement in execution time that results from the parallel architecture of this type of computer. Recommendations as to the types of tasks which are optimally suitable for this computer architecture are made, together with the improvement in execution speed to be expected. (Author)

A study compared a parallel distributed processing (PDP) model with a more traditional symbolic information processing model that accounts for early reading acquisition by human subjects. Two experimental paradigms were simulated. In one paradigm (a "savings" paradigm) subjects were divided into two groups and trained with two sets of stimuli: consistent orthographic representation of voicing, or inconsistent mapping of orthography onto voicing. A total of 32 simulated trials were generated with each model. Analysis of the savings paradigm data for the symbolic model revealed no significant main or interaction effects. Analysis of the PDP data revealed significant main and interaction effects. A second paradigm involved a forced-choice task testing subjects' ability to make use of analytic generalization. A total of eight simulated trials were generated with each model. Analysis indicated no significant difference between the symbolic model and chance performance, while the PDP model had perfect performance, indicating that the network had learned to make use of the orthography-voicing relationship implicit in the stimuli. Findings suggest that, in the domain of early reading acquisition, the problem with the PDP model approach is not that it is too weak but that it is too strong--even the simplest PDP models exhibit learning beyond what is observed in human subjects faced with similar learning tasks. (Contains 18 references. An appendix of data is attached.) (RS)

How do we assign nouns correctly to their underlying case roles in English, and how do we select an appropriate verb frame to assign these nouns to? How do we know whether a noun phrase is a modifier of a preceding noun phrase or an argument of the verb? How do we select the correct meaning of each noun in the sentence, and how do we allow content to modulate its meaning? How do we know how to handle these new nouns and verbs? In this article we describe a simulation model that addresses these questions from a perspective quite different from the conventional perspective found in Computational Linguistics. Words are treated as patterns of activation, and knowledge about them is stored in distributed form, in the connections in a large network of simple neutron-like processing units. The model exhibits considerable facility in dealing with the problems of frame selection, role assignment, disambiguation, etc, and suggests a natural way to resolve unappealing aspects of the idea that there is a fixed set of individuated case roles. So far, our simulation model can only process one clause sentences. Possible extensions to multi-clause sentences are described.

Waveform relaxation algorithms for the simulation of MOS circuits exhibit natural parallelism, arising from the intrinsic partitioning of the circuit into subcircuits which are solved separately during the iterative solution process. Investigated in this thesis is the extent to which the overall run time of a simulation can be reduced by utilizing the natural parallelism of waveform relaxation on parallel processors. Keywords: Parallel processing, Circuit simulation, Waveform relaxation, VLSI(Very Large Scab Integrated Circuits), Computerized simulation, Parallel processors, Algorithms.

A VLSI design methodology, built around the CHiP architecture, is described. The switch lattice of the CHiP architecture is the primary design abstraction. The lattice is a flexible design medium with constraints that mirror those of raw silicon. An eight point pipelined Fast Fourier Transform design, used as a running example, is of independent interest for its locally connected layout. (Author)

A VLSI design methodology, built around the CHiP architecture, is described. The switch lattice of the CHiP architecture is the primary design abstraction. The lattice is a flexible design medium with constraints that mirror those of raw silicon. An eight point pipelined Fast Fourier Transform design, used as a running example, is of independent interest for its locally connected layout. (Author)

tilak_agerwala.mpg

From the bitsavers.org collection, a scanned-in computer-related document. dec :: Books :: Digital Press :: Segall Parallel Processing the Cm* Experience 1987

From the bitsavers.org collection, a scanned-in computer-related document. dec :: Books :: Digital Press :: Segall Parallel Processing the Cm* Experience 1987

Algorithms define} as recursive functions, such as in \"pure\" LISP, are shown to have structure sufficient to distinguish between processes which must be executed in sequence and processes which may be executed in parallel. An interpreter program is presented for executing LISP programs and simultaneously computing the number of processors needed at each step of program execution in order to achieve optimum parallel processing. Sample program runs are presented to show speed-up ratios between strictly sequential and optimally parallel executions. A possible hardware organization for a parallel processing system derived from the interpreter program is presented.

In order to process very high resolution image data from spacecraft sensors, Goddard Space Flight Center commissioned the development of a Massively Parallel Processor (MPP) based upon simultaneous processing of image picture elements (pixels) rather than serial processing. It resulted in a considerable increase in computational speed. MasPar Computer Corporation's MasPar MP-1 incorporates this technology, allowing users to attack a variety of computationally-intensive problems. The MP-1 is no longer manufactured but has been replaced by the MP-2, a more advanced model.

Handling skew is one of the major challenges in query processing. In distributed computational environments such as MapReduce, uneven distribution of the data to the servers is not desired. One of the dominant measures that we want to optimize in distributed environments is communication cost. In a MapReduce job this is the amount of data that is transferred from the mappers to the reducers. In this paper we will introduce a novel technique for handling skew when we want to compute a multiway join in one MapReduce round with minimum communication cost. This technique is actually an adaptation of the Shares algorithm [Afrati et. al, TKDE 2011].

With the increase of centralization of resources in IT-infrastructure and the growing amount of cloud services, database management systems (DBMS) will be more and more outsourced to Infrastructure-as-a-Service (IaaS) providers. The outsourcing of entire databases, or the computation power for processing Big Data to an external provider also means that the provider has full access to the information contained in the database. In this article we propose a feasible solution with Order-Preserving Encryption (OPE) and further, state of the art, encryption methods to sort and process Big Data on external resources without exposing the unencrypted data to the IaaS provider. We also introduce a proof-of-concept client for Google BigQuery as example IaaS Provider.

The simulation of the propagation of electrical activity in a realistic-geometry computer model of the ventricles of the human heart using the governing reaction-diffusion equation is described. Each model point is represented by the phase 1 Luo-Rudy membrane model, appropriately modified to represent human action potentials. A separate longer-duration action potential waveform was used for the M cells found in the ventricular mid-wall. Cardiac fiber rotation across the ventricular wall was implement via an analytic equation, resulting in a spatially-varying anisotropic conductivity tensor and consequently anisotropic propagation. Since the model comprises approximately 12 million points, parallel processing was used to cut down on simulation time. The model generated acceptably normal electrocardiograms, vector cardiograms and body surface potential maps on the surface of a numerical human torso model. Interestingly, it was found that the intrinsic difference in action potential duration between M cells and other myocardial cells was greatly diminished due to electrotonic coupling.

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

The Final Proceedings for VECPAR, 4th International Meeting on Vector and Parallel Processing, 21-23 June 2000, an interdisciplinary conference covering topics in all areas of vector, parallel and distributed computing applied to a broad range of research disciplines with a focus on engineering. The principal topics include: Cellular Automata, Computational Fluid Dynamics, Crash and Structural Analysis, Data Warehousing and Data Mining, Distributed Computing and Operating Systems, Fault Tolerant Systems, Imaging and Graphics, Interconnection Networks, Languages and Tools, Numerical Methods, Parallel and Distributed Algorithms, Real-time and Embedded Systems, Reconfigurable Systems, Linear Algebra Algorithms and Software for Large Scientific Problems, Computer Organization, Image Analysis and Synthesis, and Nonlinear Problems.

The Final Proceedings for VECPAR, 4th International Meeting on Vector and Parallel Processing, 21-23 June 2000, an interdisciplinary conference covering topics in all areas of vector, parallel and distributed computing applied to a broad range of research disciplines with a focus on engineering. The principal topics include: Cellular Automata, Computational Fluid Dynamics, Crash and Structural Analysis, Data Warehousing and Data Mining, Distributed Computing and Operating Systems, Fault Tolerant Systems, Imaging and Graphics, Interconnection Networks, Languages and Tools, Numerical Methods, Parallel and Distributed Algorithms, Real-time and Embedded Systems, Reconfigurable Systems, Linear Algebra Algorithms and Software for Large Scientific Problems, Computer Organization, Image Analysis and Synthesis, and Nonlinear Problems.

The Naval Research Laboratory's (NRL) Code 7440 Production Enhancement Team at the Stennis Space Center has been tasked to develop ways to speedup hydrographic data processing at the Naval Oceanographic Office (NAVO). This paper presents the final development of a parallelized version of the Pfm_loader application customized to run on a Beowulf cluster. Parallel programming techniques have been used for years to develop processing software that does the same work in only a fraction of the time. The research in this paper focuses on the I/0 problem associated with a parallel application writing to a single physical disk. Included in our research are the original ideas that led to the first version of the parallel software, subsequent versions of the software derived from lessons learned from benchmark results, and speedup results of each version. The platform used was a custom built Linux Beowulf cluster running a standard Linux kernel and the MPICH parallel message-passing library. The underlying purpose of this software is to process hydrographic data having a complicated, multi-tiered format. The data processing involves reading tens to hundreds of files containing raw date, filtering out extraneous data values, and writing the filtered data to a single file used in additional processing. The problem is not computationally intensive, but bound by the system's file writing capability. Subsequent versions of the parallel software developed exploit the strengths of the system's hardware to write the output file in the most time efficient manner. Each software version uses advanced software architecture schemes to achieve better results. Results show that the more responsible the software was for organizing the data before writing, the better the speedup. The critical factor for writing data efficiently involved the limitation of writing data over a single I/0 controller. Our parallel software has fantastic utility where system specifications do not allow for the 7

Continuous innovations in adaptive matched-field processing (MFP) algorithms have presented significant increases in computational complexity and resource requirements that make development and use of advanced parallel processing techniques imperative. In real-time sonar systems operating in severe underwater environments, there is a high likelihood of some part of systems exhibiting defective behavior, resulting in loss of critical network, processor, and sensor elements, and degradation in beam power pattern. Such real-time sonar systems require high reliability to overcome these challenging problems. In this paper, efficient fault-tolerant parallel algorithms based on coarse-grained domain decomposition methods are developed in order to meet real-time and reliability requirements on distributed array systems in the presence of processor and sensor element failures. The performance of the fault-tolerant parallel algorithms is experimentally analyzed in terms of beamforming performance, computation time, speedup, and parallel efficiency on a distributed testbed. The performance results demonstrate that these fault-tolerant parallel algorithms can provide real-time, scalable, lightweight, and fault-tolerant implementations for adaptive MFP algorithms on distributed array systems.

Evidence has supported the idea that readers lexically process words serially (one at a time), but evidence by Mirault et al. (2018) has demonstrated a transposed word effect. This effect is where readers have difficulty deciding that sentences such as “do love you me? “are ungrammatical, in which the transposition of two adjacent words (i.e., love you) would form a grammatical sentence, compared to sentences in which the transposition of two words does not result in grammaticality (e.g. the cat white was slowly). This has been taken as evidence for the parallel lexical processing of multiple words simultaneously. Evidence has also shown that the transposed word effect can be attributed to a combination of noisy bottom-up word position coding and top-down syntactic constraints. This effect can be interpreted within serial, as opposed to parallel, reading models. The present study will examine the transposed word effect by varying type of processing for which each of the two transposed words will be presented. We aim to replicate the previous findings by presenting words presented one word following the previous word in a sentence, as opposed to on word being presented at a time. In this experiment, we manipulate sequence type. Thus, we expected that the transposed word effect in visual parallel paradigm to be replicated such that transposed words are responded to more slowly and are more error prone than control words. However, the main focus is on accuracy. In addition, we aim to compare the results of visual transposed word parallel processing with that of visual transposed word serial processing. This is to assess whether the transposed word effect occurs as a result of the integration of word n+1 may begin before the integration of word n is complete, which may allow the transposed word effect to occur (Huang & Staub, 2021) . As a result, the findings we observed may be more likely to ensue, as there is a higher likelihood that word n would not complete when the integration of word n+1 began when all words are presented in a parallel, as opposed to serial manner. If this is the case, then the transposed word effect should be numerically larger in parallel than serial.

A surface patch/wire junction EFIE method of moment algorithm, JUNCTION, developed by the University of Houston has been implemented in a transputer based parallel processing environment installed in a personal computer. This paper addresses transputer hardware and software options, the JUNCTION algorithm, techniques for parallelizing matrix analysis algorithms, and performance results. The transputer array was found to provide a flexible, low- cost, high performance desktop computing environment for method of moment analysis.... Parallel processing, Computational electromagnets, Visualization.

The Final Proceedings for VECPAR 98 3rd International Meeting on Vector and Parallel Processing, 21 June 1998-23 June 1998. This 15 an Interdisciplinary conference. Topics Include parallel and distributed computing, image processing and synthesis. real-time and embedded systems.

In the sequential world, the mapping of processes to a computer system was not a problem because of the classic Von Newman architecture. However, in the parallel world, the mapping of processes to nodes and the balancing of the load on each node becomes an issue that needs to be addressed. This problem enters software development in the implementation phase and remains an issue through the testing and system integration phases. This report describes a new method developed to improve the mapping on a hypercube system. This new hypersphere mapping approach performs an optimal mapping based on the geometry of the physical system and the communication patterns of the processes. The hypersphere mapper can map processes to nodes where the number of processes exceeds the number of nodes. Other mapping approaches rely on heuristics to cluster the communication graphs into subgraphs to accomplish this mapping. The hypersphere mapper can be instrumental in the implementation phase of software development by specifying an optimal mapping that will improve the performance of the system. This method also provides a transparent programming environment, where the programmer does not need to know about the interconnection network of the physical computer system. The hypersphere mapper was tested using simulated directed and undirected random communication graphs.

I. Progress on the behavioral and the molecular biological goals: (1) We have finished, as originally proposed, the software and first actual physical system for computer-controlled training procedures with which to shape animal behavior and to perform learning-conditioning experiments. (2) We have constructed molecular biological vectors for generating muscarinic cholinergic receptor proteins pertaining specifically to all of the five known muscarinic receptors--this work follows on previous AFOSR-funded work relating to cholinergic enhancement of associative learning 14,15,11-13. II. Progress into the implications of attractors, perturbation analysis of neurons, and the use of language theory: (3) We have developed the conceptual rationale and conducted computer experiments to show that attractor gradients provide an integrative principle that globally acts on all synapses in a network of cooperative neurons. The consequences of this are extensive, and much naturally falls out naturally, e.g: synaptic strengths are optimally set with one another; the size of the Attractors, Dissipative action, learning, Muscarinic receptors, Symbolic dynamics, Finite-state automata, Neural networks, Neuron membrane perturbation analysis.

A Fast Reduced Instruction Set Computer is designed using the Rockwell 50 GHz Baseline GaAs/AlGaAs Heterojunction Bipolar Transistor Process. Tbe goal of the project is a 1OOO NIPS integer RISC engine in the form of a multiple chip integration using MCM technology. Cell libraries and CAD tools for this effort have been created and tested. Test structures have been fabricated and tested which indicate that the general approach is viable, and all architecture chips have been completed. However, certain process deficiencies could lead to circuit performance that is slower than predicted from Rockwell supplied models by a factor of 30-50%. In spite of this, 'work-around' strategies have been devised and it is felt that the Rockwell process can still achieve the speed goal of 2 GHz clock operation. These strategies consist of altering the layout of the transistor using a smaller emitter with a larger aspect ratio, and three active edges, and some shortening of base-emitter and base colleccor separations, and variation of the wire geometries or shifting to the third level of metal for them.

A Fast Reduced Instruction Set Computer is designed using the Rockwell 50 GHz Baseline GaAs/AlGaAs Heterojunction Bipolar Transistor Process. Tbe goal of the project is a 1OOO NIPS integer RISC engine in the form of a multiple chip integration using MCM technology. Cell libraries and CAD tools for this effort have been created and tested. Test structures have been fabricated and tested which indicate that the general approach is viable, and all architecture chips have been completed. However, certain process deficiencies could lead to circuit performance that is slower than predicted from Rockwell supplied models by a factor of 30-50%. In spite of this, 'work-around' strategies have been devised and it is felt that the Rockwell process can still achieve the speed goal of 2 GHz clock operation. These strategies consist of altering the layout of the transistor using a smaller emitter with a larger aspect ratio, and three active edges, and some shortening of base-emitter and base colleccor separations, and variation of the wire geometries or shifting to the third level of metal for them.

A multiple sensor/multiple processor 3-D tracking system includes multiple sensor (camera) and DSP combinations and a controller connected so as to create a parallel computer from the multiple DSPs. The camera/DSP combinations and the controller are connected together to form a ring. For 3-D position measurement and tracking applications, each camera/DSP combination is programmed with an identical program to function as a node in a true parallel computer, and the transformation equations are solved in a distributed fashion using the entire parallel machine. The distributed processor processes the camera x and y point measurements in a distributed and parallel fashion to yield a solution to the coordinate transformation equations much more quickly than is possible with multiple camera/DSP combinations and a single processor.

Trimester 2 2022/2023

From September through November the author concentrated on the development of an Integrated Image Understanding Benchmark for computer vision architectures. Unlike previous vision benchmarks, this new benchmark is designed to test machine performance on a complete interpretation task. The task chosen will require not only that common low-level vision operations be performed, but that intermediate-level operations and interactions between operations be tested as well. In fact, the emphasis of the benchmark is on intermediate - or high-level processes controlling lower level processing in a top-down manner. The goal of the interpretation task is to recognize a modeled object in a cluttered environment. The input to the system is a set of models, any one of which may be present in the scene, and a pair of registered images. One of the images is from a black and white 8-bit intensity sensor, and the other is from a 32-bit floating-point range sensor. For the purposes of the benchmark, the images are artificially created.

To date if has been demonstrated that an experimental animal, the sea slug Pleurobranchaea, is capable of one-trial food-aversion learning, and that the muscarinic antagonist scopolamine in low doses causes an enhancement of learning. Pharmacologic binding studies using a new, 125 sub I-form of quinuclidinyl benzilate, in addition to studies using the 3 sub H-form of this ligand, have uncovered not only the classical types of muscarinic receptors that are typical of vertebrate cortex, but also a new form that is not found in other invertebrates that we have tested. Usually muscarinic receptors are found in low densities in invertebrate neural membranes, but the density of the new form in this animal's neural membranes is similar to the density of the classic receptors in mammalian cortex. Neurophysiological studies of individual neurons in small groups of identifiable neurons have shown that their activity is variable, as is the behavior that they take part in generating, and that the variability fits the definition of low-dimensional chaos. Findings show that such variability is an important feature of the emergence of adaptive responses arising from parallel, distributed neural networks in biological systems.

Schizophrenia is marked by a variety of cognitive and biological abnormalities. In the first part of this paper we describe schizophrenic cognitive deficits in three experimental tasks which tap attention and language processing abilities. We also review biological disturbances that have been reported involving the frontal lobes and the mesocortical dopamine system. In the second part of the paper we present three computer models, each of which simulates normal performance in one of the cognitive tasks described initially. These models were developed within the connectionist (or parallel distributed processing) framework. At the behavioral level, the models suggest that a disturbance in the processing of context can account for schizophrenic patterns of performance in both the attention and language-related tasks. At the same time, the models incorporate features of biological computation that address the biological processes underlying cognitive deficits. All three models incorporate a mechanism for processing context that can be identified with frontal lobe function, and a parameter that corresponds to the effects of dopamine on frontal cortex. A disturbance in this parameter is sufficient to account for schizophrenic patterns of performance in all three of the cognitive tasks simulated. Thus, the models offer an explanatory mechanism linking performance deficits to a disturbance in the processing of context which, in turn, is attributed to a reduction of dopaminergic activity in prefrontal cortex. In the General Discussion, we consider the implications of these models for our understanding of both normal and schizophrenic cognition. We conclude with a discussion of some of the general issues surrounding the modelling endeavor itself.

The purpose of this study was to evaluate the parallel processing impact of MIMD (Multiple-Instruction Multiple-Data Path) computers on Flight Simulation Software. Basic mathematical functions and arithmetic expressions from typical Flight Simulation Software were selected and run on a MIMD computer to evaluate the improvement in execution time that results from the parallel architecture of this type of computer. Recommendations as to the types of tasks which are optimally suitable for this computer architecture are made, together with the improvement in execution speed to be expected. (Author)

The research in this paper focuses on the I/O problem associated with a parallel application writing to a single physical disk. Included in our research are the original ideas that led to the first version of the parallel software, subsequent versions of the software derived from lessons learned from benchmark results, and speedup results of each version. The underlying purpose of this software is to process hydrographic data having a complicated, multi-tiered format. The data processing involves reading tens to hundreds of files containing raw data, filtering out extraneous data values, and writing the filtered data to a single file used in additional processing. The problem is not computationally intensive, but bound by the system's file writing capability. Results show that the more responsible the software was for organizing the data before writing, the better the speedup. The critical factor for writing data efficiently involved the limitation of writing data over a single I/O controller. Our parallel software has fantastic utility where system specifications do not allow for the use of parallel file systems, or writing data over multiple I/O controllers.

The PEPE Simulation Project has had the responsibility of validating the design of the MSI PEPE by functional simulation. This validation was achieved by demonstrating that the performance characteristics of the MSI PEPE are superior to those of the IC design used in the PHSD demonstrations. Toward achieving design validation, two functional simulation models were constructed; a Calibration Model and a System Verification Model. The purpose of this document is to describe the functions performed by the action sequence chains that comprise these two models.

The PEPE Simulation Project has had the responsibility of validating the design of the MSI PEPE by functional simulation. This validation was achieved by demonstrating that the performance characteristics of the MSI PEPE are superior to those of the IC design used in the PHSD demonstrations. Toward achieving design validation, two functional simulation models were constructed; a Calibration Model and a System Verification Model. The purpose of this document is to describe the functions performed by the action sequence chains that comprise these two models.

The PEPE Simulation Project has had the responsibility of validating the design of the MSI PEPE by functional simulation. This validation was achieved by demonstrating that the performance characteristics of the MSI PEPE are superior to those of the IC design used in the PHSD demonstrations. Toward achieving design validation, two functional simulation models were constructed; a Calibration Model and a System Verification Model. The purpose of this document is to describe the functions performed by the action sequence chains that comprise these two models.

This report describes the difficulties involved in writing efficient parallel programs and describes the hardware and software support currently available for generating software that utilizes processing effectively. Historically, the processing rate of single-processor computers has increased by one order of magnitude every five years. However, this pace is slowing since electronic circuitry is coming up against physical barriers. Unfortunately, the complexity of engineering and research problems continues to require ever more processing power (far in excess of the maximum estimated 3 Gflops achievable by single-processor computers). For this reason, parallel processing architectures are receiving considerable interest, since they offer high performance more cheaply than a single-processor supercomputer, such as the Cray. Keywords: Multiprocessing, Concurrent processing, Processor evaluation tools, Parallel debugging, Fluidics, Fluerics.

Computer simulations of catalytic networks. Andrade et al. (1993) have recently published the results of our first simulations, and have addressed the problem of the effect that catalytic error has in controlling system dynamics. Simulations of large networks are being designed in order examine spatio-temporal dynamics in reaction-diffusion systems. The aim is to develop visualization and analysis methods to apply large networks composed of biologically realistic neurons. Immunohistochemical studies have examined mammalian tissues that may be useful as model systems to examine distributed function in neurotransmission and neuromodulation (Soinila and Mpitsos, 1992; Soinila et al., 1992). It is necessary, as these and other publications (e.g., Mpitsos and Soinila, 1993) indicate, not only to understand neural organization in a simple animal, but also to examine the applicability of the findings to higher animals, and, if possible, to humans. Molecular biological studies of muscarinic receptors: In previous AFOSR-published work, Murray et al. (1985) and Murray and Mpitsos (1988) showed further that brief pharmacologic blocking of these receptors enhances 1-Trial associative learning. Over the past year, we have developed cloning vectors for generating fusing proteins to all of the five known muscarinic receptor subtypes in humans. Our next step is to obtaine immunofluorescent antisera to the fusion proteins in order to visually identify cells containing the different muscarinic receptors. The in-between step will be to determine the specificity of the antisera. The findings will be applicable not only to our experimental animal, but also to studies of learning and pathologies in humans.

Multidisciplinary design optimization (MDO) for large-scale engineering problems poses many challenges (e.g., the design of an efficient concurrent paradigm for global optimization based on disciplinary analyses, expensive computations over vast data sets, etc.) This work focuses on the application of distributed schemes for massively parallel architectures to MDO problems, as a tool for reducing computation time and solving larger problems. The specific problem considered here is configuration optimization of a high speed civil transport (HSCT), and the efficient parallelization of the embedded paradigm for reasonable design space identification. Two distributed dynamic load balancing techniques (random polling and global round robin with message combining) and two necessary termination detection schemes (global task count and token passing) were implemented and evaluated in terms of effectiveness and scalability to large problem sizes and a thousand processors. The effect of certain parameters on execution time was also inspected. Empirical results demonstrated stable performance and effectiveness for all schemes, and the parametric study showed that the selected algorithmic parameters have a negligible effect on performance.

The ALLSPD-3D Computational Fluid Dynamics code for reacting flow simulation was run on a set of benchmark test cases to determine its parallel efficiency. These test cases included non-reacting and reacting flow simulations with varying numbers of processors. Also, the tests explored the effects of scaling the simulation with the number of processors in addition to distributing a constant size problem over an increasing number of processors. The test cases were run on a cluster of IBM RS/60000 Model 590 workstations with ethernet arid ATM networking plus a shared memory SGI Power Challenge L workstation. The results indicate that the network capabilities significantly influence the parallel efficiency, i.e., a shared memory machine is fastest and ATM networking provides acceptable performance. The limitations of ethernet greatly hamper the rapid calculation of flows using ALLSPD-3D.

Tools and techniques were developed by Massively Parallel Technologies Inc. (MPT) which enable intrinsically non-parallel processing problems to be processed by inexpensive parallel processing architectures. The objective of this contract effort was to create a more effective method for multi-sensor searches, and toward that goal, to improve data fusion and processing capability by greater than 10 times over current capabilities (when compared to the capability as shown in a uniprocessor environment). This objective was met, and the performance speed up yielded a greater than 70 times speed up on a 127-node Howard Cascade RAIS (Redundant Array of Inexpensive Systems). The processing solution implemented is original and innovative; it can be implemented in a non-intrusive manner, yielding accurate results and efficient scaling into existing processing environments, using inexpensive off-the-shelf components. In addition a methodology has been developed that provides for rapid integration of new algorithms into the defined multi-sensor fusion processing solution.