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Chime Financial, Inc.'s Chief Operating Officer Mark Troughton and financial lawyers discussed the current state of the American payment system and the inclusion of non-bank digital payment systems. Topics included the digital divide, faster access to liquidity, the change from cash to digital payment services, and regulation of money service businesses. Sponsor: Brookings Institution

Tri 1 2018/2019

Trimester 3 - 2016 / 2017

Tri 2 – 2016/2017

Trimester 1 2017/2018

Digital Signals and Systems (May – 2017) [Question Paper | IDOL: Revised Course] april - 2017, april - 2016, april - 2015, april - 2014, april - 2013, october - 2017, october - 2016, october - 2015, october - 2014, may - 2016, may - 2017, december - 2017, 75:25 pattern, 60:40 pattern, revised course, old course, mumbai bscit study, mumbai university, bscit semester vi, bscit question paper, old question paper, previous year question paper, semester vi question paper, question paper, CBSGS, IDOL, kamal t, internet technology, digital signals and systems, data warehousing, ipr and cyber laws, project management, geographic information system

Digital Signals and Systems (May – 2017) [Question Paper | IDOL: Revised Course] april - 2017, april - 2016, april - 2015, april - 2014, april - 2013, october - 2017, october - 2016, october - 2015, october - 2014, may - 2016, may - 2017, december - 2017, 75:25 pattern, 60:40 pattern, revised course, old course, mumbai bscit study, mumbai university, bscit semester vi, bscit question paper, old question paper, previous year question paper, semester vi question paper, question paper, CBSGS, IDOL, kamal t, internet technology, digital signals and systems, data warehousing, ipr and cyber laws, project management, geographic information system

Digital Signals and Systems (May – 2017) [Question Paper | IDOL: Revised Course] april - 2017, april - 2016, april - 2015, april - 2014, april - 2013, october - 2017, october - 2016, october - 2015, october - 2014, may - 2016, may - 2017, december - 2017, 75:25 pattern, 60:40 pattern, revised course, old course, mumbai bscit study, mumbai university, bscit semester vi, bscit question paper, old question paper, previous year question paper, semester vi question paper, question paper, CBSGS, IDOL, kamal t, internet technology, digital signals and systems, data warehousing, ipr and cyber laws, project management, geographic information system

Present practices in lightning protection of aircraft deal primarily with the direct effects of lightning, such as structural damage and ignition of fuel vapors. There is increasing evidence of troublesome electromagnetic effects, however, in aircraft employing solid-state microelectronics in critical navigation, instrumentation and control functions. The potential impact of these indirect effects on critical systems such as digital fly by wire (DFBW) flight controls was studied. The results indicate a need for positive steps to be taken during the design of future fly by wire systems to minimize the possibility of hazardous effects from lightning.

Army transformation and the requirement to support two major combat operations simultaneously has placed a burden on the Army's ability to generate equipped, trained, and ready combat power on a reliable non-exhaustive cyclic model. The Army Force Generation Model (ARFORGEN) has done a great deal to alleviate that stress by dictating timelines for equipping, training, deploying, and resetting of combat units. However, when dealing with information systems that have an ever evolving capabilities timeline, the ARFORGEN process results in units deploying with information technology capabilities that may be several years old. To preclude that from happening, and to provide the best possible solution in a timely manner, Program Managers of Army Digital Systems have created innovative tools and procedures to augment the ARFORGEN Process and deliver the best possible information technology system of systems to combat units. These tools include forward presence, database managers, and an Army wide collaborative process that provides constant upgrade, even through the deployment timeline.

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This study analyzes the DCS digital transmission system and requirements; defines the wideband digital (CPMAS) Communications Performance Monitoring and Assessment requirements; defines and evaluates CPMAS alternatives; recommends a wideband digital CPMAS approach; makes recommendations for the ATEC production; sets up a plan to demonstrate feasibility of wideband digital CPMAS approach (option phase), and makes recommendations for ATEC research and development programs. The Digital Transmission System Model provides multi-link routes, a variety of station types (e.g., nodal station, branching repeater station and terminal station) transmission equipments (e.g., Radio, Key Generator, Multiplexers, Submultiplexers and service channel multiplexers), and terminations (e.g., 4 kHz (PCM derived), async digital channels, digital groups, and 16 kb/s digital subchannels). The radios used for digital transmission include DRAMA-TI-4000 multiplexer baseband section (FKV).

This research project investigated digital command, control, and communications (C3) systems of the U.S. military services to find information that could be used to help integrate U.S. Army digital C3 systems into digital units. The first part of the project identified key elements of U.S. Army digital systems and used these elements to identify similar systems in the U.S. Navy, U.S. Air Force, U.S. Marine Corps, and civilian services such as police, fire, and emergency services. Once similarities were identified, the next step was to collect information on lessons learned, best practices, training, and research that would be relevant to U.S. Army digital systems. The results found that few digital C3 were similar to U.S. Army systems, and most are still under development. The only systems that had close similarities with U.S. Army digital systems were tactical-level systems used by the U.S. Marine Corps. Consequently, agreements have been made to share research and development products between the U.S. Army and the U.S. Marine Corps. (2 tables, 21 refs.)

This Validation Summary Report describes the extent to which a specific Ada compiler conforms to the Ada Standard, ANSI/MIL-STD-1815A. This report explains all technical terms used within it and thoroughly reports the results of testing this compiler using the Ada Compiler Validation Capability. An Ada compiler must be implemented according to the Ada Standard, and any implementation-dependent features must conform to the requirements of the Ada Standard. The Ada Standard must be implemented in its entirety, and nothing can be implemented that is not in the Standard. Even though all validation Ada compilers conform to the Ada Standard, it must be understood that some differences do exist between implementations. The Ada Standard permits some implementation dependencies--for example, the maximum length of identifiers or the maximum values of integer types. Other differences between compilers result from the characteristics of particular operating systems, hardware, or implementation strategies. All the dependencies observed during the process of testing this compiler are given in this report. The information in this report is derived from the test results produced during validation testing. The validation process includes submitting a suite of standardized tests, the ACVC, as inputs to an Ada compiler and evaluating the results

This monograph examines the complexity of the Army's current digital systems. Currently the Army has an ever growing number of digital systems. These digital systems are supposedly designed to increase our Soldiers' efficiency and ability to command and control in a complex combat environment. The opposite can be argued in this paper. Designing a method for establishing the needed changes in the digital systems architecture for the Army is complex. The requirements articulated by the Army and the branches within the Army are not holistic in nature. The organizations that make the decisions and develop requirements for the digital systems are numerous and have competing ideas of what the digital solution should look like in the 21st century. The procurement and acquisition process is the underlying foundation by which we develop and purchase these digital systems. This procurement and acquisition process is a bloated and an outdated bureaucratic remnant of the industrial era. In order to gain the best that the digital era has to offer we must design a new and more resilient procurement and acquisition process The U.S. Congress has a significant responsibility to pass laws and make worthwhile reforms in our acquisition system. The solution for designing and procuring digital systems in the 21st century should be codified through the Congress and understood by the American people.

The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consist of a set of nodes connected by transistor switches with each node having a state 0.1. or X (for invalid or uninitialized), and each transistor having a state :open,closed, or indeterminate. Many characteristics of MOS circuits can be modeled accurately, including : rationed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; busses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in term of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and has been used to simulate circuits containing over 10,000 transistors. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.

Analyses are presented on a variety of topics related to the transmission of digital data. The performance of several types of Phase Shift Keyed (PSK) systems, as determined by the relationship of the error probability to signal-to-noise ratio, is examined. Coherent, differentially coherent, binary and m-state PSK systems, and the effects of frequency offset, cross-talk and thermal noise on the performance of these systems are considered. The performance of m-state differentially coherent multiplexed PSK data links operating over a Rayleigh fading tropospheric scatter link is analyzed. The properties of impulse noise are examined and the effect of impulse noise on digital systems using close packed codes are investigated. Moment detection, which refers to a decision technique based on the use of temporal moments is investigated both analytically and experimentally.

Analyses are presented on a variety of topics related to the transmission of digital data. The performance of several types of Phase Shift Keyed (PSK) systems, as determined by the relationship of the error probability to signal-to-noise ratio, is examined. Coherent, differentially coherent, binary and m-state PSK systems, and the effects of frequency offset, cross-talk and thermal noise on the performance of these systems are considered. The performance of m-state differentially coherent multiplexed PSK data links operating over a Rayleigh fading tropospheric scatter link is analyzed. The properties of impulse noise are examined and the effect of impulse noise on digital systems using close packed codes are investigated. Moment detection, which refers to a decision technique based on the use of temporal moments is investigated both analytically and experimentally.

This item represents an oral argument audio file as scraped from a U.S. Government website by Free Law Project.

This item represents a case in PACER, the U.S. Government's website for federal case data. If you wish to see the entire case, please consult PACER directly.

Contents: Propagation Constraints to Reliable Digital Communications, Recent Progress in Propagation Measurements and Propagation Models, Recent Progress in Propagation Measurements and Propagation Models, Channel Simulation, Signal Processing Technology, and Signalling and Sounding Schemes for Reliable Digital Communications.

Contents: Propagation Constraints to Reliable Digital Communications, Recent Progress in Propagation Measurements and Propagation Models, Recent Progress in Propagation Measurements and Propagation Models, Channel Simulation, Signal Processing Technology, and Signalling and Sounding Schemes for Reliable Digital Communications.

The Memorandum describes the types of error that can occur in airborne digital magnetic recording systems, and the problems associated with the correction of these errors on medium and high packing density single track systems. Some methods whereby record/replay errors on single track systems may be detected and corrected are explained, and a description is given of a system using these principles. (Author)

This study analyzed currently available data specifically related to the reliability of digital avionic systems. It examined the relationships between reliability and airworthiness standards, maintenance programs, integrity, and safety. Reliability data were obtained on both air carrier and general aviation digital systems within the following categories: navigation, communications, flight instruments, flight data, and autopilot and flight controls. The analyses focused on identifying the relationships between performance of digital avionics and the following variables of interest: failure rate, system category, system design, and system application. The relationships of reliability to existing airworthiness standards, maintenance programs, integrity, and safety are also presented. The data presented indicate that digital systems are capable of performing more reliably than comparable analog systems. The data suggest that a mean time between removal in excess of 2,000 hours is generally achievable through digital design. It is also shown that the number of removals of digital units remains, on the average, twice the number of confirmed failures, as has historically been the case for analog units. During the data collection process, it was found that there are differences in reliability-reporting formats between airlines and between avionics manufacturers. The variations generate some difficulty in developing a composite representation of the reliability of digital avionics. In addition, although the advent of digital technology has enhanced the functional capabilities of avionics, the user community expressed some concern regarding aspects of the implementation, use, and maintenance of digital systems.

This study analyzed currently available data specifically related to the reliability of digital avionic systems. It examined the relationships between reliability and airworthiness standards, maintenance programs, integrity, and safety. Reliability data were obtained on both air carrier and general aviation digital systems within the following categories: navigation, communications, flight instruments, flight data, and autopilot and flight controls. The analyses focused on identifying the relationships between performance of digital avionics and the following variables of interest: failure rate, system category, system design, and system application. The relationships of reliability to existing airworthiness standards, maintenance programs, integrity, and safety are also presented. The data presented indicate that digital systems are capable of performing more reliably than comparable analog systems. The data suggest that a mean time between removal in excess of 2,000 hours is generally achievable through digital design. It is also shown that the number of removals of digital units remains, on the average, twice the number of confirmed failures, as has historically been the case for analog units. During the data collection process, it was found that there are differences in reliability-reporting formats between airlines and between avionics manufacturers. The variations generate some difficulty in developing a composite representation of the reliability of digital avionics. In addition, although the advent of digital technology has enhanced the functional capabilities of avionics, the user community expressed some concern regarding aspects of the implementation, use, and maintenance of digital systems.

Digital Communication Systems

We use a model that was first introduced by Preparata, Metze, and Chien. In this model, a digital system is partitioned into a certain number of units, each of which can be at one of two possible states, fault-free and faulty. A configuration of a system is an assignment of either the fault-free or the faulty state to each unit in the system. We assume that each unit in the system possesses a certain amount of computational resources to enable it to test is a binary signal which depends on the state of the testing and the tested units. In particular, we assume that: (1) if a fault-free unit is tested by a fault-free unit, a signal 0 will be generated; (2) if a faulty unit is tested by a fault-free unit, a signal 1 will be generated; and (3) if a fault-free or a faulty unit is tested by a faulty unit, either a signal 0 or a signal 1 will be generated. (In other words, the signal generated by a faulty testing unit is completely unreliable.) A diagnosis experiment is one in which every unit tests all the units it is capable of testing once. The outcomes of the tests are referred to as a syndrome.

A high performance digital electrohydraulic stepper actuator was designed, fabricated, and tested. Performance and space requirements were derived from design studies for the Multipurpose Missile. The design provides digital interface compatibility while achieving the required performance characteristics. The actuator performed well at the rated conditions of 140 degrees per second and 1333 inch pounds load. No load speed achieved during test was over twice as great as the 250 degrees per second required. Stall torque exceeded the 2000 inch pounds design requirement. The actuator has yet to be evaluated at the 600 F design environment.

The University of Maryland has developed a specialized data system for the operational and the recording requirements of the Multi-Aperture Amplitude Interferometer. The primary role of this data system is the operation of the University of Maryland Array Photometer. This array photometer is essentially an extremely sensitive low light level television, with special requirements on its various modes of operation. Thus we shall discuss its ability to take long integration pictures, scan rapidly, and partially scan an array. This procedure will increase the dynamic range by a factor as large as one hundred and will increase the frame rate up as high as several thousand frames per second. Several other special techniques which have been developed for the University of Maryland Array Photometer will be discussed and some of the results described. (Author)

This is the final report to be prepared for the Material Test Division, Instrumentation and Methodology Branch, of the U.S. Army Electronic Proving Ground, Fort Huachuca, Arizona, under Contract DAEA18-74-A-0271/0004 and 0005. The purpose of the contract was to undertake a program of applied research to provide comprehensive standards and test methodologies, including recommended instrumentation, data collection, data reduction, and analysis criteria for digital communications systems and equipment. The primary objective was to identify meaningful, measurable parameters, recommend instrumentation required to obtain these measurements, and to provide analysis methodologies and performance criteria. The scope of the overall study was focused on those measurable parameters that are purely digital in nature or relate directly to the digital error performance of the equipment or system being examined. The purpose of this portion of the final report is to provide a brief summary of the previous reports arranged according to specific areas of interest. The general categories are Digital communications Theory, Evaluation of System Performance, Instrumentation and Methodologies, Reduction of Test Time, and A New Technique for Equipment alignment. Each area within these general categories is referenced to the specific sections in the earlier reports where complete detailed information can be obtained.(Author)

The Defense Mapping Agency Aerospace Center has developed a program to exploit digital image technology for the advancement of mapping, charting, and geodesy. Primary investigations include image processing, analysis, and display techniques, and computer image generation. A dramatic impact has been made in the ability to produce, analyze, and validate digital data bases produced by the Defense Mapping Agency by applying state-of-the-art digital image technology concepts to the development of new interactive prototype and production cartographic systems. (Author)

The Defense Mapping Agency Aerospace Center has developed a program to exploit digital image technology for the advancement of mapping, charting, and geodesy. Primary investigations include image processing, analysis, and display techniques, and computer image generation. A dramatic impact has been made in the ability to produce, analyze, and validate digital data bases produced by the Defense Mapping Agency by applying state-of-the-art digital image technology concepts to the development of new interactive prototype and production cartographic systems. (Author)

The recent proliferation of color displays has accentuated the need for a metric of color contrast which can be used to predict human operator performance. To obtain the data for forming a metric of color contrast, one needs the capability of presenting a broad range of colors in varying geometric arrangements. This report describes an approach to developing the capability to display colors of known chromaticity using a color digital image processing system. This report covers the development of measurement technique and software used in characterizing the display system, the reduction of spectroradiometric data, the use of color mixing equations for color digital image processing systems, and the development of display system software. (Author)

The recent proliferation of color displays has accentuated the need for a metric of color contrast which can be used to predict human operator performance. To obtain the data for forming a metric of color contrast, one needs the capability of presenting a broad range of colors in varying geometric arrangements. This report describes an approach to developing the capability to display colors of known chromaticity using a color digital image processing system. This report covers the development of measurement technique and software used in characterizing the display system, the reduction of spectroradiometric data, the use of color mixing equations for color digital image processing systems, and the development of display system software. (Author)

Studies were performed in three aspects of radar system digital signal processors viz., (1) theoretical analysis of the quantization errors in fixed-point and floating-point realizations of quadrature channel processor, (2) simulation analysis of the processors, and (3) floating-point hardware considerations. These efforts included the effects of (1) the quantization errors of the quadrature channel analog-to-digital converters, (2) the finite word length coefficients used in the moving target indicator, (3) the vector magnitude approximation involved in the residue calculation, and (4) the truncation of products and/or sums. Numerous graphical presentations are given for the average value and variance of the error at the processor output.

Techniques are developed to estimate power gain, delay, signal-to-noise ratio, and mean square error in digital computer simulations of lowpass and bandpass systems. The techniques are applied to analog and digital communications. The signal-to-noise ratio estimates are shown to be maximum likelihood estimates in additive white Gaussian noise. The methods are seen to be especially useful for digital communication systems where the mapping from the signal-to-noise ratio to the error probability can be obtained. Simulation results show the techniques developed to be accurate and quite versatile in evaluating the performance of many systems through digital computer simulation.

System architectures which incorporate fail operative flight guidance functions within a total integrated avionics complex are described. It is shown that the mixture of flight critical and nonflight critical functions within a common computer complex is an efficient solution to the integration of navigation, guidance, flight control, display, and flight management. Interfacing subsystems retain autonomous capability to avoid vulnerability to total avionics system shutdown as a result of only a few failures.

No Description

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.