Verification by error modeling - Info and Reading Options
using testing techniques in hardware verification
By Katarzyna Radecka
"Verification by error modeling" was published by Kluwer Academic Publishers in 2003 - Boston, it has 216 pages and the language of the book is English.
“Verification by error modeling” Metadata:
- Title: Verification by error modeling
- Author: Katarzyna Radecka
- Language: English
- Number of Pages: 216
- Publisher: Kluwer Academic Publishers
- Publish Date: 2003
- Publish Location: Boston
“Verification by error modeling” Subjects and Themes:
- Subjects: ➤ Computer-aided design - Error analysis (Mathematics) - Integrated circuits - Verification - Very large scale integration - TECHNOLOGY & ENGINEERING - Circuits - COMPUTERS - Logic Design - Engineering - Logic - VLSI & ULSI - Electrical engineering - Electronics - Integrated circuits, very large scale integration - Computer software, verification - Error analysis (mathematics)
Edition Specifications:
- Pagination: xiv, 216 p. :
Edition Identifiers:
- The Open Library ID: OL19290691M - OL8701524W
- Online Computer Library Center (OCLC) ID: 53276421
- Library of Congress Control Number (LCCN): 2003062044
- ISBN-10: 1402076525
- All ISBNs: 1402076525
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