Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits - Info and Reading Options
By Martin Wirnshofer
"Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits" was published by Springer Netherlands in 2013 - Dordrecht, it has 83 pages and the language of the book is English.
“Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits” Metadata:
- Title: ➤ Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits
- Author: Martin Wirnshofer
- Language: English
- Number of Pages: 83
- Publisher: Springer Netherlands
- Publish Date: 2013
- Publish Location: Dordrecht
“Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits” Subjects and Themes:
- Subjects: ➤ Systems engineering - Control - Electronic Circuits and Devices - Circuits and Systems - Energy Efficiency (incl. Buildings) - Simulation and Modeling - Computer simulation - Physics
Edition Specifications:
- Format: [electronic resource] /
- Pagination: XI, 83 p. 53 illus.
Edition Identifiers:
- The Open Library ID: OL27094101M - OL19909303W
- ISBN-13: 9789400761964
- All ISBNs: 9789400761964
AI-generated Review of “Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits”:
"Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits" Table Of Contents:
- 1- 1 Introduction
- 2- 2 Sources of Variation
- 3- 3 Related Work
- 4- 4 Adaptive Voltage Scaling by In-situ Delay Monitoring
- 5- 5 Design of In-situ Delay Monitors
- 6- 6 Modeling the AVS Control Loop
- 7- 7 Evaluation of the Pre-Error AVS Approach
- 8- 8 Conclusion
- 9- A Appendix
- 10- A.1 Mathematical Derivation: Path Delay under Local Variations
- 11- A.2 2-D DCT Transform
- 12- References.
"Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits" Description:
The Open Library:
Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.
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