SystemVerilog for Verification - Info and Reading Options
A Guide to Learning the Testbench Language Features
By Chris Spear
"SystemVerilog for Verification" was published by Springer in 2012 and the language of the book is English.
“SystemVerilog for Verification” Metadata:
- Title: SystemVerilog for Verification
- Author: Chris Spear
- Language: English
- Publisher: Springer
- Publish Date: 2012
“SystemVerilog for Verification” Subjects and Themes:
- Subjects: ➤ Systems engineering - Circuits and Systems - Computer input-output equipment - Computers - Engineering - Computer-Aided Engineering (CAD, CAE) and Design - Computer engineering - Computer-aided design - Electrical engineering - Verification - Integrated circuits - SystemVerilog (Computer hardware description language) - Verilog (computer hardware description language) - Object-oriented programming (computer science) - Computer hardware description languages - Object-oriented programming (Computer science) - Ingénierie
Edition Specifications:
- Weight: 0.922
- Pagination: xliv, 464
Edition Identifiers:
- The Open Library ID: OL37142008M - OL19905515W
- ISBN-13: 9781461407140
- All ISBNs: 9781461407140
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