SystemVerilog for Verification - Info and Reading Options

"SystemVerilog for Verification" Table Of Contents:

• 1- Verification Guidelines
• 2- The Verification Process
• 3- Testing at Different Levels
• 4- The Verification Plan
• 5- The Verification Methodology Manual
• 6- Basic Testbench Functionality
• 7- Directed Testing
• 8- Methodology Basics
• 9- Constrained-Random Stimulus
• 10- What Should You Randomize?
• 11- Device and Environment Configuration
• 12- Input Data
• 13- Protocol Exceptions, Errors, and Violations
• 14- Delays and Synchronization
• 15- Parallel Random Testing
• 16- Functional Coverage
• 17- Feedback from Functional Coverage to Stimulus
• 18- Testbench Components
• 19- Layered Testbench
• 20- A Flat Testbench
• 21- The Signal and Command Layers
• 22- The Functional Layer
• 23- The Scenario Layer
• 24- The Test Layer and Functional Coverage
• 25- Building a Layered Testbench
• 26- Creating a Simple Driver
• 27- Simulation Environment Phases
• 28- Maximum Code Reuse
• 29- Testbench Performance
• 30- Conclusion
• 31- Exercises
• 32- Data Types
• 33- Built-In Data Types
• 34- The Logic Type
• 35- 2-State Data Types
• 36- Fixed-Size Arrays
• 37- Declaring and Initializing Fixed-Size Arrays
• 38- The Array Literal
• 39- Basic Array Operations - for and foreach
• 40- Basic Array Operations - Copy and Compare
• 41- Bit and Array Subscripts, Together at Last
• 42- Packed Arrays
• 43- Packed Array Examples
• 44- Choosing Between Packed and Unpacked Arrays
• 45- Dynamic Arrays
• 46- Queues
• 47- Associative Arrays
• 48- Array Methods
• 49- Array Reduction Methods
• 50- Array Locator Methods
• 51- Array Sorting and Ordering
• 52- Building a Scoreboard with Array Locator Methods
• 53- Choosing a Storage Type
• 54- Flexibility
• 55- Memory Usage
• 56- Speed
• 57- Data Access
• 58- Choosing the Best Data Structure
• 59- Creating New Types with typedef
• 60- Creating User-Defined Structures
• 61- Creating a Struct and a New Type
• 62- Initializing a Structure
• 63- Making a Union of Several Types
• 64- Packed Structures
• 65- Choosing Between Packed and Unpacked Structures
• 66- Packages
• 67- Type Conversion
• 68- The Static Cast
• 69- The Dynamic Cast
• 70- Streaming Operators
• 71- Enumerated Types
• 72- Defining Enumerated Values
• 73- Routines for Enumerated Types
• 74- Converting To and From Enumerated Types
• 75- Constants
• 76- Strings
• 77- Expression Width
• 78- Conclusion
• 79- Exercises
• 80- Procedural Statements and Routines
• 81- Procedural Statements
• 82- Tasks, Functions, and Void Functions
• 83- Routine Overview
• 84- Routine Begin ... End Removed
• 85- Routine Arguments
• 86- C-style Routine Arguments
• 87- Argument Direction
• 88- Advanced Argument Types
• 89- Default Value for an Argument
• 90- Passing Arguments by Name
• 91- Common Coding Errors
• 92- Returning from a Routine
• 93- The Return Statement
• 94- Returning an Array from a Function
• 95- Local Data Storage
• 96- Automatic Storage
• 97- Variable Initialization
• 98- Time Values
• 99- Time Units and Precision
• 100- Time Literals
• 101- Time and Variables
• 102- $time vs. $realtime
• 103- Conclusion
• 104- Exercises
• 105- Connecting the Testbench and Design
• 106- Separating the Testbench and Design
• 107- Communication Between the Testbench and the DUT
• 108- Communication with Ports
• 109- The Interface Construct
• 110- Using an Interface to Simplify Connections
• 111- Connecting Interfaces and Ports
• 112- Grouping Signals in an Interface Using Modports
• 113- Using Modports with a Bus Design
• 114- Creating an Interface Monitor
• 115- Interface Trade-Offs
• 116- More Information and Examples
• 117- Logic vs. Wire in an Interface
• 118- Stimulus Timing
• 119- Controlling Timing of Synchronous Signals with a Clocking Block
• 120- Timing Problems in Verilog
• 121- Testbench-Design Race Condition
• 122- The Program Block and Timing Regions
• 123- Specifying Delays Between the Design and Testbench
• 124- Interface Driving and Sampling
• 125- Interface Synchronization
• 126- Interface Signal Sample
• 127- Interface Signal Drive
• 128- Driving Interface Signals Through a Clocking Block
• 129- Bidirectional Signals in the Interface
• 130- Specifying Delays in Clocking Blocks
• 131- Program Block Considerations
• 132- The End of Simulation
• 133- Why Are Always Blocks Not Allowed in a Program?
• 134- The Clock Generator
• 135- Connecting It All Together
• 136- An Interface in a Port List Must Be Connected
• 137- Top-Level Scope
• 138- Program-Module Interactions
• 139- SystemVerilog Assertions
• 140- Immediate Assertions
• 141- Customizing the Assertion Actions
• 142- Concurrent Assertions
• 143- Exploring Assertions
• 144- The Four-Port ATM Router
• 145- ATM Router with Ports
• 146- ATM Top Level Module with Ports
• 147- Using Interfaces to Simplify Connections
• 148- ATM Interfaces
• 149- ATM Router Model Using an Interface
• 150- ATM Top-Level Module with Interfaces
• 151- ATM Testbench with Interface
• 152- The Ref Port Direction
• 153- Conclusion
• 154- Exercises
• 155- Basic OOP
• 156- Introduction
• 157- Think of Nouns, Not Verbs
• 158- Your First Class
• 159- Where to Define a Class
• 160- OOP Terminology
• 161- Creating New Objects
• 162- Handles and Constructing Objects
• 163- Custom Constructor
• 164- Separating the Declaration and Construction
• 165- The Difference Between new() and new[]
• 166- Getting a Handle on Objects
• 167- Object Deallocation
• 168- Using Objects
• 169- Class Methods
• 170- Defining Methods Outside of the Class
• 171- Static Variables vs. Global Variables
• 172- A Simple Static Variable
• 173- Accessing Static Variables Through the Class Name
• 174- Initializing Static Variables
• 175- Static Methods
• 176- Scoping Rules
• 177- What Is This?
• 178- Using One Class Inside Another
• 179- How Big or Small Should My Class Be?
• 180- Compilation Order Issue
• 181- Understanding Dynamic Objects
• 182- Passing Objects and Handles to Methods
• 183- Modifying a Handle in a Task
• 184- Modifying Objects in Flight
• 185- Arrays of Handles
• 186- Copying Objects
• 187- Copying an Object with the new Operator
• 188- Writing Your Own Simple Copy Function
• 189- Writing a Deep Copy Function
• 190- Packing Objects to and from Arrays Using Streaming Operators
• 191- Public vs. Local
• 192- Straying Off Course
• 193- Building a Testbench
• 194- Conclusion
• 195- Exercises
• 196- Randomization
• 197- Introduction
• 198- What to Randomize
• 199- Device Configuration
• 200- Environment Configuration
• 201- Primary Input Data
• 202- Encapsulated Input Data
• 203- Protocol Exceptions, Errors, and Violations
• 204- Delays
• 205- Randomization in SystemVerilog
• 206- Simple Class with Random Variables
• 207- Checking the Result from Randomization
• 208- The Constraint Solver
• 209- What Can Be Randomized?
• 210- Constraint Details
• 211- Constraint Introduction
• 212- Simple Expressions
• 213- Equivalence Expressions
• 214- Weighted Distributions
• 215- Set Membership and the inside Operator
• 216- Using an Array in a Set
• 217- Bidirectional Constraints
• 218- Implication Constraints
• 219- Equivalence Operator
• 220- Solution Probabilities
• 221- Unconstrained
• 222- Implication
• 223- Implication and Bidirectional Constraints
• 224- Guiding Distribution with solve ... before
• 225- Controlling Multiple Constraint Blocks
• 226- Valid Constraints
• 227- In-Line Constraints
• 228- The pre_randomize and post_randomize Functions
• 229- Building a Bathtub Distribution
• 230- Note on Void Functions
• 231- Random Number Functions
• 232- Constraints Tips and Techniques
• 233- Constraints with Variables
• 234- Using Nonrandom Values
• 235- Checking Values Using Constraints
• 236- Randomizing Individual Variables
• 237- Turn Constraints Off and On
• 238- Specifying a Constraint in a Test Using In-Line Constraints
• 239- Specifying a Constraint in a Test with External Constraints
• 240- Extending a Class
• 241- Common Randomization Problems
• 242- Use Signed Variables with Care
• 243- Solver Performance Tips
• 244- Choose the Right Arithmetic Operator to Boost Efficiency
• 245- Iterative and Array Constraints
• 246- Array Size
• 247- Sum of Elements
• 248- Issues with Array Constraints
• 249- Constraining Individual Array and Queue Elements
• 250- Generating an Array of Unique Values
• 251- Randomizing an Array of Handles
• 252- Atomic Stimulus Generation vs. Scenario Generation
• 253- An Atomic Generator with History
• 254- Random Array of Objects
• 255- Combining Sequences
• 256- Randsequence
• 257- Random Control
• 258- Introduction to randcase
• 259- Building a Decision Tree with randcase
• 260- Random Number Generators
• 261- Pseudorandom Number Generators
• 262- Random Stability - Multiple Generators
• 263- Random Stability and Hierarchical Seeding
• 264- Random Device Configuration
• 265- Conclusion
• 266- Exercises
• 267- Threads and Interprocess Communication
• 268- Working with Threads
• 269- Using fork ... join and begin ... end
• 270- Spawning Threads with fork ... join none
• 271- Synchronizing Threads with fork ... join any
• 272- Creating Threads in a Class
• 273- Dynamic Threads
• 274- Automatic Variables in Threads
• 275- Waiting for All Spawned Threads
• 276- Sharing Variables Across Threads
• 277- Disabling Threads
• 278- Disabling a Single Thread
• 279- Disabling Multiple Threads
• 280- Disable a Task that Was Called Multiple Times
• 281- Interprocess Communication
• 282- Events
• 283- Blocking on the Edge of an Event
• 284- Waiting for an Event Trigger
• 285- Using Events in a Loop
• 286- Passing Events
• 287- Waiting for Multiple Events
• 288- Semaphores
• 289- Semaphore Operations
• 290- Semaphores with Multiple Keys
• 291- Mailboxes
• 292- Mailbox in a Testbench
• 293- Bounded Mailboxes
• 294- Unsynchronized Threads Communicating with a Mailbox
• 295- Synchronized Threads Using a Bounded Mailbox and a Peek
• 296- Synchronized Threads Using a Mailbox and Event
• 297- Synchronized Threads Using Two Mailboxes
• 298- Other Synchronization Techniques
• 299- Building a Testbench with Threads and IPC
• 300- Basic Transactor
• 301- Configuration Class
• 302- Environment Class
• 303- Test Program
• 304- Conclusion
• 305- Exercises
• 306- Advanced OOP and Testbench Guidelines
• 307- Introduction to Inheritance
• 308- Basic Transaction
• 309- Extending the Transaction Class
• 310- More OOP Terminology
• 311- Constructors in Extended Classes
• 312- Driver Class
• 313- Simple Generator Class
• 314- Blueprint Pattern
• 315- The Environment Class
• 316- A Simple Testbench
• 317- Using the Extended Transaction Class
• 318- Changing Random Constraints with an Extended Class
• 319- Downcasting and Virtual Methods
• 320- Downcasting with $cast
• 321- Virtual Methods
• 322- Signatures and Polymorphism
• 323- Constructors are Never Virtual
• 324- Composition, Inheritance, and Alternatives
• 325- Deciding Between Composition and Inheritance
• 326- Problems with Composition
• 327- Problems with Inheritance
• 328- A Real-World Alternative
• 329- Copying an Object
• 330- Specifying a Destination for Copy
• 331- Abstract Classes and Pure Virtual Methods
• 332- Callbacks
• 333- Creating a Callback
• 334- Using a Callback to Inject Disturbances
• 335- A Quick Introduction to Scoreboards
• 336- Connecting to the Scoreboard with a Callback
• 337- Using a Callback to Debug a Transactor
• 338- Parameterized Classes
• 339- A Simple Stack
• 340- Sharing Parameterized Classes
• 341- Parameterized Class Suggestions
• 342- Static and Singleton Classes
• 343- Dynamic Class to Print Messages
• 344- Singleton Class to Print Messages
• 345- Configuration Database with Static Parameterized Class
• 346- Creating a Test Registry
• 347- Test Registry with Static Methods
• 348- Test Registry with a Proxy Class
• 349- UVM Factory Build
• 350- Conclusion
• 351- Exercises
• 352- Functional Coverage
• 353- Gathering Coverage Data
• 354- Coverage Types
• 355- Code Coverage
• 356- Functional Coverage
• 357- Bug Rate
• 358- Assertion Coverage
• 359- Functional Coverage Strategies
• 360- Gather Information, Not Data
• 361- Only Measure What You Are Going to Use
• 362- Measuring Completeness
• 363- Simple Functional Coverage Example
• 364- Anatomy of a Cover Group
• 365- Defining a Cover Group in a Class
• 366- Triggering a Cover Group
• 367- Sampling Using a Callback
• 368- Cover Group with a User-Defined Sample Argument List
• 369- Cover Group with an Event Trigger
• 370- Triggering on a SystemVerilog Assertion
• 371- Data Sampling
• 372- Individual Bins and Total Coverage
• 373- Creating Bins Automatically
• 374- Limiting the Number of Automatic Bins Created
• 375- Sampling Expressions
• 376- User-Defined Bins Find a Bug
• 377- Naming the Cover Point Bins
• 378- Conditional Coverage
• 379- Creating Bins for Enumerated Types
• 380- Transition Coverage
• 381- Wildcard States and Transitions
• 382- Ignoring Values
• 383- Illegal Bins
• 384- State Machine Coverage
• 385- Cross Coverage
• 386- Basic Cross Coverage Example
• 387- Labeling Cross Coverage Bins
• 388- Excluding Cross Coverage Bins
• 389- Excluding Cover Points from the Total Coverage Metric
• 390- Merging Data from Multiple Domains
• 391- Cross Coverage Alternatives
• 392- Generic Cover Groups
• 393- Pass Cover Group Arguments by Value
• 394- Pass Cover Group Arguments by Reference
• 395- Coverage Options
• 396- Per-Instance Coverage
• 397- Cover Group Comment
• 398- Coverage Threshold
• 399- Printing the Empty Bins
• 400- Coverage Goal
• 401- Analyzing Coverage Data
• 402- Measuring Coverage Statistics During Simulation
• 403- Conclusion
• 404- Exercises
• 405- Advanced Interfaces
• 406- Virtual Interfaces with the ATM Router
• 407- The Testbench with Just Physical Interfaces
• 408- Testbench with Virtual Interfaces
• 409- Connecting the Testbench to an Interface in a Port List
• 410- Connecting the Test to an Interface with an XMR
• 411- Connecting to Multiple Design Configurations
• 412- A Mesh Design
• 413- Using Typedefs with Virtual Interfaces
• 414- Passing Virtual Interface Array Using a Port
• 415- Parameterized Interfaces and Virtual Interfaces
• 416- Procedural Code in an Interface
• 417- Interface with Parallel Protocol
• 418- Interface with Serial Protocol
• 419- Limitations of Interface Code
• 420- Conclusion
• 421- Exercises
• 422- A Complete SystemVerilog Testbench
• 423- Design Blocks
• 424- Testbench Blocks
• 425- Alternate Tests
• 426- Your First Test - Just One Cell
• 427- Randomly Drop Cells
• 428- Conclusion
• 429- Exercises
• 430- Interfacing with C/C++
• 431- Passing Simple Values
• 432- Passing Integer and Real Values
• 433- The import Declaration
• 434- Argument Directions
• 435- Argument Types
• 436- Importing a Math Library Routine
• 437- Connecting to a Simple C Routine
• 438- A Counter with Static Storage
• 439- The chandle Data Type
• 440- Representation of Packed Values
• 441- 4-State Values
• 442- Converting from 2-State to 4-State
• 443- Connecting to C++
• 444- The Counter in C++
• 445- Static Methods
• 446- Communicating with a Transaction-Level C++ Model
• 447- Simple Array Sharing
• 448- Single-Dimension Arrays - 2-State
• 449- Single-Dimension Arrays - 4-State
• 450- Open Arrays
• 451- Basic Open Array
• 452- Open Array Methods
• 453- Passing Unsized Open Arrays
• 454- Packed Open Arrays in DPI
• 455- Sharing Composite Types
• 456- Passing Structures Between SystemVerilog and C
• 457- Passing Strings Between SystemVerilog and C
• 458- Pure and Context Imported Methods
• 459- Communicating from C to SystemVerilog
• 460- A Simple Exported Function
• 461- C Function Calling a SystemVerilog Function
• 462- C Task Calling a SystemVerilog Task
• 463- Calling Methods in Objects
• 464- The Meaning of Context
• 465- Setting the Scope for an Imported Routine
• 466- Connecting Other Languages
• 467- Conclusion
• 468- Exercises
• 469- References
• 470- Index

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