Modeling, Control And Steady State Analysis Of Back To Back VSC HVDC System - Info and Reading Options
By IJOER Engineering journal
"Modeling, Control And Steady State Analysis Of Back To Back VSC HVDC System" and the language of the book is English.
“Modeling, Control And Steady State Analysis Of Back To Back VSC HVDC System” Metadata:
- Title: ➤ Modeling, Control And Steady State Analysis Of Back To Back VSC HVDC System
- Author: IJOER Engineering journal
- Language: English
“Modeling, Control And Steady State Analysis Of Back To Back VSC HVDC System” Subjects and Themes:
- Subjects: ➤ Inner loops Controller - outer loops Controller - Vector Control - VSC HVDC - engineering journal - International Journal - Journal - Research Journal
Edition Identifiers:
- Internet Archive ID: IJOERFEB201628
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"Modeling, Control And Steady State Analysis Of Back To Back VSC HVDC System" Description:
The Internet Archive:
<p class="MsoNormal" style="margin-top:0.05pt;margin-right:7.75pt;margin-bottom:0.0001pt;margin-left:8.05pt;text-align:justify;line-height:115%;"><span><span style="font-size:10pt;line-height:115%;">This paper proposes a dynamic model of a VSC (voltage source converter) based Back to Back HVDC system and its control technique. From the system model, the corresponding relationship between the controlling and the controlled variables of the VSC is determined. The vector control technique is used to control the working of converters. The control structure consists of outer control loop and inner control loop. The outer loop controller controls the active <span style="letter-spacing:0.25pt;">and </span>reactive power separately. The inner loop controller which is a fast working controller provides the reference <span style="letter-spacing:0.1pt;">d- </span>axis and q- axis voltages which are required by the PWM for generating the triggering pulse. The validity of the model and the feasibility of the control method have been proved by the simulation results. <span style="letter-spacing:0.2pt;">In </span>this paper the system performance is studied under steady state<span style="letter-spacing:-0.15pt;"></span>condition.</span></span></p>
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