"Microsoft Research Video 103748: Candidate Talk: Software And Architectural Techniques For Cache Leakage Reduction In Nanometer-scale Embedded Systems" - Information and Links:

Microsoft Research Video 103748: Candidate Talk: Software And Architectural Techniques For Cache Leakage Reduction In Nanometer-scale Embedded Systems - Info and Reading Options

"Microsoft Research Video 103748: Candidate Talk: Software And Architectural Techniques For Cache Leakage Reduction In Nanometer-scale Embedded Systems" and the language of the book is English.


“Microsoft Research Video 103748: Candidate Talk: Software And Architectural Techniques For Cache Leakage Reduction In Nanometer-scale Embedded Systems” Metadata:

  • Title: ➤  Microsoft Research Video 103748: Candidate Talk: Software And Architectural Techniques For Cache Leakage Reduction In Nanometer-scale Embedded Systems
  • Author:
  • Language: English

Edition Identifiers:

  • Internet Archive ID: ➤  Microsoft_Research_Video_103748

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"Microsoft Research Video 103748: Candidate Talk: Software And Architectural Techniques For Cache Leakage Reduction In Nanometer-scale Embedded Systems" Description:

The Internet Archive:

<p>Energy consumption is a fundamental barrier in taking full advantage of integration capability of today and future semiconductor manufacturing technology. With technology scaling to nanometer dimensions, leakage (static) power is gaining a bigger share in total power consumption, and furthermore, variation is increasing in transistor parameters (such as gate length, width, and threshold voltage, V<sub>th</sub> ) such that leakage as well as delay varies even among SRAM cells located within the same die.</p><p>We present our recent research activities and results on reducing cache leakage energy under real-time constraints in processor-based embedded systems. This includes /(i)/ reducing leakage energy in instruction cache by taking advantage of value-dependence of SRAM leakage due to within-die V<sub>th</sub> variation, /(ii)/ using asymmetric SRAM designs that leak less when storing a 0, and then renaming register-operands of instructions so as to increase number of zeros in instruction-cache, and hence, to reduce leakage,/ (iii)/ shifting the delay-distribution curve of SRAM cells toward higher delays without impacting delay, capacity, or timing-yield of the entire cache by adding extra cache-ways or by adding spare rows/columns of SRAM.</p><p>We also briefly review our other works in Kyushu University on estimating and reducing static and dynamic power consumption of real-time embedded systems and also overview our methodology developed in Sharif University of Technology for efficient hardware-software implementation of object-oriented embedded applications</p><div class="fs30">©2008 Microsoft Corporation. All rights reserved.</div>

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  • Added Date: 2014-02-18 19:59:17

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