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Functional Verification of Dynamically Reconfigurable FPGA-Based Systems - Info and Reading Options

"Functional Verification of Dynamically Reconfigurable FPGA-Based Systems" was published by Springer in 2014 - Cham, it has 216 pages and the language of the book is English.


“Functional Verification of Dynamically Reconfigurable FPGA-Based Systems” Metadata:

  • Title: ➤  Functional Verification of Dynamically Reconfigurable FPGA-Based Systems
  • Authors:
  • Language: English
  • Number of Pages: 216
  • Publisher: Springer
  • Publish Date:
  • Publish Location: Cham

“Functional Verification of Dynamically Reconfigurable FPGA-Based Systems” Subjects and Themes:

Edition Specifications:

  • Weight: 5.287

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"Functional Verification of Dynamically Reconfigurable FPGA-Based Systems" Description:

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This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them; Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects; Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described; Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, ModelSim simulator, Verilog/VHDL design language, etc. …)

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