Embedded Computer Systems : Architectures, Modeling, and Simulation - Info and Reading Options

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Intro -- Preface -- SAMOS 2019 Organization -- Contents -- System Design Space Exploration -- Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments -- 1 Introduction -- 2 Related Work -- 3 Processor Architecture Organizations -- 3.1 2-Stage Pipeline AVR8 (8-Bit) Processor -- 3.2 Multi-Cycle NEO430 (16-Bit) Processor -- 3.3 5-Stage Pipeline MIPS32 (32-Bit) Processor -- 3.4 4-Stage Pipeline VLIW-MIPS (32-Bit) Processor -- 3.5 Transport-Triggered Architecture (32-Bit) Processor -- 3.6 Fully Configurable Divider Co-processor -- 4 Evaluation -- 4.1 Target Application -- 4.2 TTA Configurations -- 4.3 Trade-off Analysis -- 5 Conclusion -- References -- CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures -- 1 Introduction -- 2 Related Work -- 3 Target Architecture and Coherency Region Manager -- 3.1 CRM: Architectural Design and Functionality -- 3.2 RBCC-malloc(): Runtime Working Set Adaptability -- 4 Hardware Implementation -- 5 Experimental Evaluation -- 6 Conclusion and Future Work -- References -- RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM*-14pt -- 1 Introduction -- 2 RRAM Background -- 3 Related Work -- 4 Modelling of RRAM -- 4.1 RRAM Cell and Selector -- 4.2 Crossbar Array -- 4.3 RRAM Architecture -- 4.4 Area Model -- 4.5 Energy Model -- 5 Results and Discussion -- 6 Conclusion and Future Work -- References -- Deep Learning Optimization -- Efficient Dynamic Device Placement for Deep Neural Network Training on Heterogeneous Systems -- Abstract -- 1 Introduction -- 2 Definition -- 2.1 Co-location Operations -- 2.2 Operations Cost -- 2.3 The Optimization Problem -- 3 Algorithms -- 3.1 Partitioned Boolean Quadratic Programming -- 3.2 Critical Earliest Finish Time Algorithm -- 4 Design Methodology

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