"DTIC ADA420740: Chip Multiprocessors Offer An Economical, Scalable Architecture For Future Microprocessors, Thread-Level Speculation Support Allows Them To Speed Up Past Software" - Information and Links:

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"DTIC ADA420740: Chip Multiprocessors Offer An Economical, Scalable Architecture For Future Microprocessors, Thread-Level Speculation Support Allows Them To Speed Up Past Software" and the language of the book is English.


“DTIC ADA420740: Chip Multiprocessors Offer An Economical, Scalable Architecture For Future Microprocessors, Thread-Level Speculation Support Allows Them To Speed Up Past Software” Metadata:

  • Title: ➤  DTIC ADA420740: Chip Multiprocessors Offer An Economical, Scalable Architecture For Future Microprocessors, Thread-Level Speculation Support Allows Them To Speed Up Past Software
  • Author: ➤  
  • Language: English

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  • Internet Archive ID: DTIC_ADA420740

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The Hydra chip multiprocessor (CMP) integrates four MIP-based processors and their primary caches on a single chip together with a shared secondary cache. A standard CMP offers implementation and performance advantages compared to wide-issue superscalar design& However, it must be programmed with a more complicated parallel programming model to obtain maximum performance. To simplify parallel programming, the Hydra CMP supports thread-level speculation and memory renaming, a paradigm that allows performance similar to a uniprocessor of comparable die area on integer programs. This article motivates the design of a CMP, describes the architecture of the Hydra design with a focus on its speculative thread support, and describes our prototype implementation.

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