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"DTIC ADA158367: Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches To PLA (Programmable Logic Array) Design." and the language of the book is English.


“DTIC ADA158367: Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches To PLA (Programmable Logic Array) Design.” Metadata:

  • Title: ➤  DTIC ADA158367: Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches To PLA (Programmable Logic Array) Design.
  • Author: ➤  
  • Language: English

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  • Internet Archive ID: DTIC_ADA158367

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"DTIC ADA158367: Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches To PLA (Programmable Logic Array) Design." Description:

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Part 1: Scalable CMOS design rules are developed for the MOSIS community to facilitate fabrication from a single design at 3 microns and 1.3 microns VHSIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technology are explored in this project. Three different CMOS PLA circuit styles are described: the large PLA uses a gated OR plane and is useful for a system with large number of inputs; the moderate PLA and the small PLA are ripple varieties with the former having the capability of handling a larger number of inputs than the latter. Path Programmable Logic (PPL), which is a folded form of a PLA, is also studied. A symbolic form of representation is developed and future PPL development activities are discussed. The PPL approach has a size and flexibility advantage over the other PLA approaches - except in applications requiring large PLA's.

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