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This article is from BMC Psychiatry , volume 12 . Abstract Background: Semi-structured interview scales for psychosis are the gold standard approach to assessing psychotic and other symptoms. However, such assessments have limitations such as recall bias, averaging, insensitivity to change and variable interrater reliability. Ambulant, real-time self-report assessment devices may hold advantages over interview measures, but it needs to be shown that the data thus collected are valid, and the collection method is acceptable, feasible and safe. We report on a monitoring system for the assessment of psychosis using smartphone technology. The primary aims were to: i) assess validity through correlations of item responses with those on widely accepted interview assessments of psychosis, and ii) examine compliance to the procedure in individuals with psychosis of varying severity. Methods: A total of 44 participants (acute or remitted DSM-4 schizophrenia and related disorders, and prodromal) completed 14 branching self-report items concerning key psychotic symptoms on a touch-screen mobile phone when prompted by an alarm at six pseudo-random times, each day, for one week. Face to face PANSS and CDS interviews were conducted before and after the assessment period blind to the ambulant data. Results: Compliance as defined by completion of at least 33% of all possible data-points over seven days was 82%. In the 36 compliant participants, 5 items (delusions, hallucinations, suspiciousness, anxiety, hopelessness) showed moderate to strong (rho 0.6-0.8) associations with corresponding items from interview rating scales. Four items showed no significant correlation with rating scales: each was an item based on observable behaviour. Ambulant ratings showed excellent test-retest reliability and sensitivity to change. Conclusions: Ambulatory monitoring of symptoms several times daily using smartphone software applications represents a feasible and valid way of assessing psychotic phenomena for research and clinical management purposes. Further evaluation required over longer assessment periods, in clinical trials and service settings.

This article is from BMC Psychiatry , volume 12 . Abstract Background: Semi-structured interview scales for psychosis are the gold standard approach to assessing psychotic and other symptoms. However, such assessments have limitations such as recall bias, averaging, insensitivity to change and variable interrater reliability. Ambulant, real-time self-report assessment devices may hold advantages over interview measures, but it needs to be shown that the data thus collected are valid, and the collection method is acceptable, feasible and safe. We report on a monitoring system for the assessment of psychosis using smartphone technology. The primary aims were to: i) assess validity through correlations of item responses with those on widely accepted interview assessments of psychosis, and ii) examine compliance to the procedure in individuals with psychosis of varying severity. Methods: A total of 44 participants (acute or remitted DSM-4 schizophrenia and related disorders, and prodromal) completed 14 branching self-report items concerning key psychotic symptoms on a touch-screen mobile phone when prompted by an alarm at six pseudo-random times, each day, for one week. Face to face PANSS and CDS interviews were conducted before and after the assessment period blind to the ambulant data. Results: Compliance as defined by completion of at least 33% of all possible data-points over seven days was 82%. In the 36 compliant participants, 5 items (delusions, hallucinations, suspiciousness, anxiety, hopelessness) showed moderate to strong (rho 0.6-0.8) associations with corresponding items from interview rating scales. Four items showed no significant correlation with rating scales: each was an item based on observable behaviour. Ambulant ratings showed excellent test-retest reliability and sensitivity to change. Conclusions: Ambulatory monitoring of symptoms several times daily using smartphone software applications represents a feasible and valid way of assessing psychotic phenomena for research and clinical management purposes. Further evaluation required over longer assessment periods, in clinical trials and service settings.

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vii, 160 p. ; 26 cm

ix, 384 p. : 28 cm

ix, 384 p. : 28 cm

ix, 384 p. : 28 cm

ix, 384 p. : 28 cm

ix, 384 p. : 28 cm

ix, 384 p. : 28 cm

This paper documents a two-and-a-half year software development project of the Combat Systems Configuration Management Branch of the Combat Systems Department at Naval Surface Warfare Center, Dahlgren Division (NSWCDD), at Dahlgren, Virginia. The author simultaneously managed two AEGIS Configuration Control Engineering Status System (ACCESS) software development projects and pursued a master's degree in Software Engineering Technical Management through the National Technological University sponsored by NSWCDD. The paper describes lessons learned and practical experience gained by the author in managing a software development project to successful completion. The narrative includes methods that worked and ones that did not work. Critical success factors that the author considers most important to satisfactory software development are: (1) structured and documented iterative life cycle development methodology; (2) implementation of software engineering repeatable processes; (3) highly-motivated, technically experienced dedicated team; (4) continuous and substantial customer involvement; (5) self-directed, empowered management style; and (6) experienced and committed project leader.

This paper documents a two-and-a-half year software development project of the Combat Systems Configuration Management Branch of the Combat Systems Department at Naval Surface Warfare Center, Dahlgren Division (NSWCDD), at Dahlgren, Virginia. The author simultaneously managed two AEGIS Configuration Control Engineering Status System (ACCESS) software development projects and pursued a master's degree in Software Engineering Technical Management through the National Technological University sponsored by NSWCDD. The paper describes lessons learned and practical experience gained by the author in managing a software development project to successful completion. The narrative includes methods that worked and ones that did not work. Critical success factors that the author considers most important to satisfactory software development are: (1) structured and documented iterative life cycle development methodology; (2) implementation of software engineering repeatable processes; (3) highly-motivated, technically experienced dedicated team; (4) continuous and substantial customer involvement; (5) self-directed, empowered management style; and (6) experienced and committed project leader.

This paper documents a two-and-a-half year software development project of the Combat Systems Configuration Management Branch of the Combat Systems Department at Naval Surface Warfare Center, Dahlgren Division (NSWCDD), at Dahlgren, Virginia. The author simultaneously managed two AEGIS Configuration Control Engineering Status System (ACCESS) software development projects and pursued a master's degree in Software Engineering Technical Management through the National Technological University sponsored by NSWCDD. The paper describes lessons learned and practical experience gained by the author in managing a software development project to successful completion. The narrative includes methods that worked and ones that did not work. Critical success factors that the author considers most important to satisfactory software development are: (1) structured and documented iterative life cycle development methodology; (2) implementation of software engineering repeatable processes; (3) highly-motivated, technically experienced dedicated team; (4) continuous and substantial customer involvement; (5) self-directed, empowered management style; and (6) experienced and committed project leader.

This report investigates a model order reduction technique developed by Dr Bruce Moore of the University of Toronto, as applied to the B-52E flutter control problem currently under study by the Air Force Flight Dynamics Laboratory. The algorithm, which is based upon singular value analysis, is applied to the full twenty-fourth order model yielding an internally balanced representation which is balanced with respect to controllability and observability properties. The system is reduced in order, and comparisons are made between the Moore algorithm model and that obtained via a method used by the Air Force Flight Dynamics Laboratory. In addition to this investigation, an interactive program is presented which contains the model order reduction algorithm. Other capabilities include: estimation of the condition number with respect to inversion, singular value and condition number plotting vs. sample time for discrete time controllability, observability, and Hankel matrices, frequency response generation, and various special coordinate system transformation. (Author)

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This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.