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This is the final report on the findings of the USAF/OSR grant to support collaboration between INRIA (FR), University of Kaiserslautern (DE) and Virginia Tech (VA, USA) on research entitled 'Co-Modeling of Safety-Critical Multi-threaded Embedded Software for Multi-Core Embedded Platforms. In this project, we consider and integrate two different model-based design flows that are based on synchronous languages: The first design flow starts with a polychronous model that is in some sense a process network whose nodes are triggered whenever input values are available. \\

This is the final report on the findings of the AFRL funded project A Formal Approach to the Provably Correct Synthesis of Mission Critical Embedded Software for Multi-core Platforms. In this work we enhanced the theory of a formal modeling language based specifications, namely MRICDF. We demonstrated an implementation of a software specification and code synthesis tool based on MRICDF. The work entails new synthesis algorithms, characterization of specifications, formal proof techniques for proving the correctness preservation property of the refinement steps in our step-wise refinement oriented synthesis technique, multi-core code synthesis, endowing the specification with platform specific worst case execution times to check real-time schedulability, and some case studies.

Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for control software. Given the formal model of a plant as a Discrete Time Linear Hybrid System and the implementation specifications (that is, number of bits in the Analog-to-Digital (AD) conversion) correct-by-construction control software can be automatically generated from System Level Formal Specifications of the closed loop system (that is, safety and liveness requirements), by computing a suitable finite abstraction of the plant. With respect to given implementation specifications, the automatically generated code implements a time optimal control strategy (in terms of set-up time), has a Worst Case Execution Time linear in the number of AD bits $b$, but unfortunately, its size grows exponentially with respect to $b$. In many embedded systems, there are severe restrictions on the computational resources (such as memory or computational power) available to microcontroller devices. This paper addresses model based synthesis of control software by trading system level non-functional requirements (such us optimal set-up time, ripple) with software non-functional requirements (its footprint). Our experimental results show the effectiveness of our approach: for the inverted pendulum benchmark, by using a quantization schema with 12 bits, the size of the small controller is less than 6% of the size of the time optimal one.

In this work, we address the synthesis of embedded software for sensor nodes in two important, specialized contexts. In the first context, an optimization framework is designed to automate the design space exploration of application-specific wireless sensor networks in order to adjust configuration parameters for deriving a streamlined overall implementation of the system. The framework is built around the particle swarm optimization technique and adapted especially for the optimization of a line-crossing detection application. The second synthesis context draws from the potential effectiveness of using dataflow graphs for the implementation of DSP applications for sensor nodes to explore a context switching mechanism facilitating concurrent execution of multiple dataflow graphs on a single embedded processor. Our model for context switch implementation uses compile-time information to optimize runtime scheduling. Simulation results in both cases support the applicability of the adopted approaches for optimized operation of application-specific sensor nodes.