Downloads & Free Reading Options - Results

This report summarizes the results associated with instrumentation purchased under DURIP contract F49620-98-1-0263 in support of AFOSR/DARPA MURI Program on 'Multivariable Control, Simulation, Optimization, and Signal Processing for the Microlithographic Process'. This project is generally concerned with the application of systems techniques to the lithographic sequence used for patterning integrated circuits at very small dimensions (less than 250 nanometers). This complex sequence is comprised of photoresist processing, mask design, and optical illumination steps. Lithography is a major technological area that may impede the continued increase in integrated circuit density (Moore's Law).

This thesis is concerned with distributed control and coordination of networks consisting of multiple, potentially mobile, agents. This is motivated mainly by the emergence of large scale networks characterized by the lack of centralized access to information and time-varying connectivity. Control and optimization algorithms deployed in such networks should be completely distributed, relying only on local observations and information, and robust against unexpected changes in topology such as link failures. We will describe protocols to solve certain control and signal processing problems in this setting. We will demonstrate that a key challenge for such systems is the problem of computing averages in a decentralized way. Namely, we will show that a number of distributed control and signal processing problems can be solved straightforwardly if solutions to the averaging problem are available. The rest of the thesis will be concerned with algorithms for the averaging problem and its generalizations. We will (i) derive the fastest known averaging algorithms in a variety of settings and subject to a variety of communication and storage constraints (ii) prove a lower bound identifying a fundamental barrier for averaging algorithms (iii) propose a new model for distributed function computation which reflects the constraints facing many large-scale networks, and nearly characterize the general class of functions which can be computed in this model.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This briefing describes the effort to implement advanced embedded signal processing for the MK 92 Fire Control System (FCS) Combined Antenna System's (CAS) search DSP with a focus on Open Architecture. The end goal of this effort was to achieve a low cost open architectural reconfigurable and generic DSP. A team of both US and international partners was assembled from LMC, INDRA Sistemas, and CSPI. LMC acted as the system design agent with responsibility for the definition of the COTS architecture, technical requirements and the MK 92 FCS integration. Indra s responsibility was for the software development that included design, implementation and test of embedded DSP. CSPI responsibilities included the development of the radar real-time hardware and interfaces for MK 92.

This article is from Sensors (Basel, Switzerland) , volume 14 . Abstract The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

A prototype expert system for the treatment of stochastic control and nonlinear signal processing problems is described with several illustrative examples. The system is written in MACSYMA, LISP, and PROLOG. It accepts user input in natural language or symbolic form; it carries out the basic analysis of the user's problem in symbolic form (e.g., computing the Bellman dynamic programming equation for stochastic control problems or the Zakai equation and the estimation Lie algebra or likelihood ratio for nonlinear filtering problems); and it produces output in the form of automatically generated FORTRAN code for the final numerical reduction of the problem. The system also has a module using PROLOG which can check the well-posedness (existence and uniqueness) of certain classes of linear and nonlinear partial differential equations specified in symbolic form by computing a natural Sobolev space for the solutions and verifying classical existence and uniqueness criteria for the given equation using MACSYMA for the computations and PROLOG for the logical analysis. Sample sessions with three of the modules of the system are presented to illustrate its operation. The status of the system and plans for its further development are described.

High Speed linear signal processing in digital systems is protected efficiently by algorithmic fault-tolerance employing real block or convolutional codes. The main signal processing operation functions normally while parity samples derived from the input data are compared against corresponding parity associated with the output samples. The parity computations and comparisons providing error detection are performed in parallel with the normal signal processing, guaranteeing no speed degradation. Real block codes are used to protect processing finite length input and output segments whereas real convolutional codes are natural for protecting a continuous input and output streams of samples. The corresponding parity values are compared considering difference threshold to account for numerical roundoff and quantization effects. A mean-square error criterion is used in analyzing the parity comparison process. Errors due to temporary and permanent hardware failures as well as numerical roundoff and quantization noise are allowed simultaneously in the main processing system, and the parity calculation and comparison subassemblies.

High Speed linear signal processing in digital systems is protected efficiently by algorithmic fault-tolerance employing real block or convolutional codes. The main signal processing operation functions normally while parity samples derived from the input data are compared against corresponding parity associated with the output samples. The parity computations and comparisons providing error detection are performed in parallel with the normal signal processing, guaranteeing no speed degradation. Real block codes are used to protect processing finite length input and output segments whereas real convolutional codes are natural for protecting a continuous input and output streams of samples. The corresponding parity values are compared considering difference threshold to account for numerical roundoff and quantization effects. A mean-square error criterion is used in analyzing the parity comparison process. Errors due to temporary and permanent hardware failures as well as numerical roundoff and quantization noise are allowed simultaneously in the main processing system, and the parity calculation and comparison subassemblies.

High Speed linear signal processing in digital systems is protected efficiently by algorithmic fault-tolerance employing real block or convolutional codes. The main signal processing operation functions normally while parity samples derived from the input data are compared against corresponding parity associated with the output samples. The parity computations and comparisons providing error detection are performed in parallel with the normal signal processing, guaranteeing no speed degradation. Real block codes are used to protect processing finite length input and output segments whereas real convolutional codes are natural for protecting a continuous input and output streams of samples. The corresponding parity values are compared considering difference threshold to account for numerical roundoff and quantization effects. A mean-square error criterion is used in analyzing the parity comparison process. Errors due to temporary and permanent hardware failures as well as numerical roundoff and quantization noise are allowed simultaneously in the main processing system, and the parity calculation and comparison subassemblies.

This research is concerned with the use of neural architectures and fuzzy expert systems in nonlinear system identification and in the control of such systems. In particular, on-line identification/modeling is considered. The research has resulted in a technique where the network can evolve (in size) in time-so as to provide an optimal model/controller. Also an adaptive algorithm, which is less sensitive to initial values of the weights and the learning rate, has been developed. We have also established a common framework between neural networks and fuzzy expert systems and developed a neuro-fuzzy architecture that retains the best of the two areas. The use of the architectures and the adaptation algorithm has been demonstrated on a number of applications.

Thesis advisor, M. A. Morgan

The objective of this Multidisciplinary University Research Initiative (MURI) program is to apply multivariable control, simulation, optimization and signal processing techniques to the microlithography sequence.

We give a brief survey of the types of acoustic waves that propagate in piezoelectric crystals, touching upon some of the most useful crystal cuts, and some of the practical structures currently used. Materials that may substitute for quartz are considered. Equivalent network structures are dealt with for the characterization of devices, and examples of typical responses achieved for bulk, surface, and shallow bulk configurations are given.

The work established the viability of a fiber-optic approach for low-loss true time delay of wideband RF signals for phased-array antenna (PAA) beamsteering. In this approach an optical carrier modulated by the RF signal of interest is launched into a delay-line fiber composed of optical Bragg reflection gratings written holographically into the core of a single-mode fiber. The beam is steered by tuning the optical carrier wavelength for reflection from the appropriate grating. The fiber Bragg grating writing performance meets and exceeds PAA requirements. We demonstrated: (1) a time delay accuracy of approximately 2 ps (20 Ps verified); (2) a wavelength writing accuracy for Bragg gratings of 0.04 microns absolute, 0.01 nm relative; (3) a sidelobe suppression of 50 dBe at 2 nm channels and 60 dBe at 3 nm channels. We produced a 4-bit, 16 grating true time delay element which includes an optical circulator. An analytical model, which includes chirp, was developed that predicts both the optical and RF response for the fiber optic Bragg grating.

This thesis describes the development of computer algorithms for experimental measurement control and subsequent signal processing of transient signatures to synthesize scattering impulse responses of scale model targets. The theories behind transient scattering are considered in order to construct the algorithms. Up-to-date hardware and software technology are selectively implemented to optimize the resultant signal to noise ratio. The detailed explanation of the hardware and software operation is provided. A noise model for the system is also discussed. Measurement and programming validations are described, where comparisons are made with numerical computations for transient scattering by selected canonical targets. Results are documented for further research in the transient scattering problem. Keywords include: Radar cross section, Transient, Scattering, and Signature.