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This Reconfigurable Computing (RC) or Adaptive Computing System (ACS) program focused on the development of both reconfigurable computing platforms and the associated programming support environments to demonstrate the viability of RC. This was demonstrated by exploring the ability to program RCs in a main/integrated C application program and by investigating new, partially reconfigurable technology. A Xilinx 4000 Field Programmable Gate Array (FPGA) series board and a Xilinx 6200 FPGA-based board were developed as pant of this effort. The C compiler technology was developed more for a hardware pragma-based implementation, which leveraged hardware macro libraries and worked quite effectively. The Xilinx 6200 board was interesting from the standpoint that the 6200 FPGAs are partially reconfigurable. The shortfalls of this product family include poor chip design/manufacture, resulting in the inability to utilize a good portion of the FPGA logic resources. Another shortfall is a lack of functional programming tools. In spite of these problems, the team was able to exercise the partial reconfigurability of the devices by developing programming tools of their own.

Communication is an essential skill for every military officer. Their jobs are accomplished through communication This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. The research builds on previous work which implemented a false radar imaging algorithm on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that the SRC-6E provides and effective solution for implementations with greater than 64 range bins. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times. The algorithm test code is included in the appendices.

Boolean functions with high algebraic immunity (AI) are vital in reducing the possibility of utilizing algebraic attacks to break an encryption system. Simple algorithms exist to compute the AI of a given n-variable Boolean function, but the time required to test a large number of functions is much greater on conventional computing systems. AI was computed for all functions through n = 5 using the SRC-6. AI was also computed for n = 5 using a C algorithm. The SRC-6 performed 4.86 times faster than a conventional processor for this computation. It is believed that this is the first enumeration of all 5-variable functions with respect to AI. Monte Carlo trials were performed for n = 6, both on the SRC-6 and utilizing a C algorithm on a conventional processor. These trials provided the first known distribution of AI for 6-variable functions. Some algorithms for computing AI require a conversion between the truth table form of the function and its algebraic normal form. The first known Verilog implementation of a reduced transeunt triangle was developed for this conversion. This reduced form requires many fewer gates and has (n) delay versus (2) n delay for a full transeunt triangle.

Formal models of adaptive reconfiguration were developed. It allowed determining the value of the performance criteria of reconfigurable computing system. A new approach of reducing the critical execution time of parallel algorithms was proposed by removing reconfiguration time overheads from the critical path of algorithm`s graph. Program model of proposed means for adaptive tasks mapping on reconfigurable FPGA computing structure

Computational science applications and advanced scientific computing have made tremendous gains in the past decade. Researchers are regularly employing the power of large computing systems and parallel processing to tackle larger and more complex problems in all of the physical sciences. For the past decade or so, most of this growth in computing power has been free with increased efficiency more-or-less governed by Moore's Law. However, increases in performance are becoming harder to achieve due to the complexity of the parallel computing platforms and the software required for these systems. Reconfigurable computing, or heterogeneous computing, is offering some hope to the scientific computing community as a means to continued growth in computing capability. This paper offers a glimpse of the hardware and software associated with this new technology and discusses how the new paradigm functions for computational science.

This report describes the development of a new field programmable gate array (FPGA) device that enables dynamic reconfiguration, the changing of hardware logic during normal system operation. The Context Switching Reconfigurable (CSRC) FPGA is capable of storing four configurations on-chip and switching between them on a single clock cycle basis. Configurations can be loaded while other contexts are active, and a powerful cross-context data sharing mechanism has bee implemented. This feature allows data to be saved on the device while other programs (context) may operate on the data. This report provides the details of the two-phase development of the CSRC device. The first phase involved the development of a small prototype integrated circuit (IC) version of the CSRC technology. This IC served both as a concept validation tool and platform for acquiring empirical data about the performance enhancements afforded by this new technology. The subsequent phase entailed the development and fabrication of a large IC (greater capacity) with several additional features. Both the prototype and the larger more capable final device are full custom IC designs designated and fabricated on National Semiconductor's .35u line.

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Many software systems have been successfully implemented using an agent paradigm which employs a number of independent entities that communicate with one another to achieve a common goal. The distributed nature of such a paradigm makes it an excellent candidate for use in high speed reconfigurable computing hardware environments such as those present in modem FPGA's. In this paper, a distributed genetic algorithm that can be applied to the agent based reconfigurable hardware model is introduced. The effectiveness of this new algorithm is evaluated by comparing the quality of the solutions found by the new algorithm with those found by traditional genetic algorithms. The performance of a reconfigurable hardware implementation of the new algorithm on an FPGA is compared to traditional single processor implementations.

With microprocessors hitting the power wall, alternative architectures are receiving substantial attention. Two factors make FPGAs promising, particularly for high performance computing applications: (i) the potential for thousand-fold parallelism, and (ii) the embedding of control into logic, which enables payload to be delivered every cycle. In this talk we will describe work in building FPGA-based accelerators for computational biology and bioinformatics. We find that, while there is potential for enormous speedup, achieving it demands both selection of appropriate applications and unusually careful design. Beginning with the applications: these include processing of biological sequences (both comparison and analysis), computations involving of microarray (gene chip) data, modeling of molecular interaction, and molecular dynamics simulations. Although low-precision computations are most amenable to acceleration, we also examine applications that typically use floating point. Success with these applications comes from specific design methods. These methods fall into four broad categories: restructuring applications to make use of a different processor model; taking advantage of fine-grained parallelism in computations and memory access; using non-standard arithmetic types and operations that map well into FPGA fabric; and finally, reconsidering application design issues. The latter include methods for ensuring that applications are flexible, scalable, and at least somewhat portable. ©2007 Microsoft Corporation. All rights reserved.

http://media.ccc.de/browse/congress/2014/31c3_-_6412_-_en_-_saal_6_-_201412272030_-_towards_general_purpose_reconfigurable_computing_on_novena_-_stars_-_andy_isaacson.html The Novena open source laptop contains a FPGA, but free software support for FPGAs is lacking and requires root access to the hardware. stars, Andy Isaacson Help us caption & translate this video! http://amara.org/v/FuHT/ Source: https://www.youtube.com/watch?v=BM1eWRwZDcA Uploader: media.ccc.de

With microprocessors hitting the power wall, alternative architectures are receiving substantial attention. Two factors make FPGAs promising, particularly for high performance computing applications: (i) the potential for thousand-fold parallelism, and (ii) the embedding of control into logic, which enables payload to be delivered every cycle. In this talk we will describe work in building FPGA-based accelerators for computational biology and bioinformatics. We find that, while there is potential for enormous speedup, achieving it demands both selection of appropriate applications and unusually careful design. Beginning with the applications: these include processing of biological sequences (both comparison and analysis), computations involving of microarray (gene chip) data, modeling of molecular interaction, and molecular dynamics simulations. Although low-precision computations are most amenable to acceleration, we also examine applications that typically use floating point. Success with these applications comes from specific design methods. These methods fall into four broad categories: restructuring applications to make use of a different processor model; taking advantage of fine-grained parallelism in computations and memory access; using non-standard arithmetic types and operations that map well into FPGA fabric; and finally, reconsidering application design issues. The latter include methods for ensuring that applications are flexible, scalable, and at least somewhat portable. ©2007 Microsoft Corporation. All rights reserved.

With microprocessors hitting the power wall, alternative architectures are receiving substantial attention. Two factors make FPGAs promising, particularly for high performance computing applications: (i) the potential for thousand-fold parallelism, and (ii) the embedding of control into logic, which enables payload to be delivered every cycle. In this talk we will describe work in building FPGA-based accelerators for computational biology and bioinformatics. We find that, while there is potential for enormous speedup, achieving it demands both selection of appropriate applications and unusually careful design. Beginning with the applications: these include processing of biological sequences (both comparison and analysis), computations involving of microarray (gene chip) data, modeling of molecular interaction, and molecular dynamics simulations. Although low-precision computations are most amenable to acceleration, we also examine applications that typically use floating point. Success with these applications comes from specific design methods. These methods fall into four broad categories: restructuring applications to make use of a different processor model; taking advantage of fine-grained parallelism in computations and memory access; using non-standard arithmetic types and operations that map well into FPGA fabric; and finally, reconsidering application design issues. The latter include methods for ensuring that applications are flexible, scalable, and at least somewhat portable. ©2007 Microsoft Corporation. All rights reserved.

This report covers the period from October 1, 1987 through September 30, 1988, the first year under the contract. The objective of this effort is to define and evaluate new approaches to two-dimensional arrays of reconfigurable optical interconnections for optical computing. The emphasis is on optically controlled optical beam directors or switches which can be fabricated into high density 2-D arrays. The proposed applications in optical neural computers and other types of optical computers require reconfiguration speeds on the order of microseconds. The emphasis is therefore on devices and nonlinear optical materials with response times of microseconds but with the potential for high packing density. The approach to this research has two components: i. nonlinear optical materials; and ii. optically controlled optical switching devices which can be integrated into 2-D arrays. The materials work stresses the transport assisted optical nonlinear materials since this is the only class of materials which exhibit a sufficiently large nonlinearity, in the response time required, and with a relatively low optical energy required. In these materials, optically excited electric charge is separated by an electric field to create a space charge field which reduces the total electric field.

The field of micro-electronics is well known for its extremely high rate of change: components such as microprocessors, microcontrollers, and ASICs (Application-Specific Integrated Circuits), are replaced by new models every few years. This high rate of change is a mixed blessing for system designers. On the one hand, it allows them to address increasingly difficult problems with increasingly capable components; on the other hand, it means that any system built only a few years ago now contains old and obsolete parts. Thus system maintenance gradually becomes very difficult, if not impossible. System design is a complex undertaking, as systems can contain from just a few to many thousands of components, and most modern systems contain software as well as hardware. Yet, any particular system is normally produced in vastly lower volume than its components, and more importantly, a system's life cycle is almost never well aligned with the life cycle of the components from which it is constructed. These factors combine to make it prohibitively expensive to update systems at the rate dictated by their component integrated circuits. As a result, it is typically the earliest innovators who find themselves holding large numbers of legacy systems, systems which can no longer be incrementally upgraded and will eventually fall into disrepair.

Although reconfigurable computing promises huge performance benefits for a wide range of different applications, there are many factors that have limited its effectiveness so far. Perhaps most concerning, current generation commercial FPGA architectures and design tools simply do not provide adequate support for these types of applications. In this talk we will discuss the details of reconfigurable computing and FPGA architectures. I will present some of the architectural and CAD tool limitations that reconfigurable computing applications pose and discuss some solutions that I have developed: register-enhanced architectures, pipeline-aware timing-driven placement, and pipeline-aware routing. ©2008 Microsoft Corporation. All rights reserved.

This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. A false-target radar-imaging algorithm was chosen and implemented on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that the implementation of the algorithm does not provide an effective solution when executed on the SRC-6E. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times. The algorithm test code and collected data are included as appendices.

Although reconfigurable computing promises huge performance benefits for a wide range of different applications, there are many factors that have limited its effectiveness so far. Perhaps most concerning, current generation commercial FPGA architectures and design tools simply do not provide adequate support for these types of applications. In this talk we will discuss the details of reconfigurable computing and FPGA architectures. I will present some of the architectural and CAD tool limitations that reconfigurable computing applications pose and discuss some solutions that I have developed: register-enhanced architectures, pipeline-aware timing-driven placement, and pipeline-aware routing. ©2008 Microsoft Corporation. All rights reserved.

Future science missions will require the use of multiple spacecraft with multiple sensor nodes autonomously responding and adapting to a dynamically changing space environment. The acquisition of random scientific events will require rapidly changing network topologies, distributed processing power, and a dynamic resource management strategy. Optimum utilization and configuration of spacecraft communications and navigation resources will be critical in meeting the demand of these stringent mission requirements. There are two important trends to follow with respect to NASA's (National Aeronautics and Space Administration) future scientific missions: the use of multiple satellite systems and the development of an integrated space communications network. Reconfigurable computing and communication systems may enable versatile adaptation of a spacecraft system's resources by dynamic allocation of the processor hardware to perform new operations or to maintain functionality due to malfunctions or hardware faults. Advancements in FPGA (Field Programmable Gate Array) technology make it possible to incorporate major communication and network functionalities in FPGA chips and provide the basis for a dynamically reconfigurable communication system. Advantages of higher computation speeds and accuracy are envisioned with tremendous hardware flexibility to ensure maximum survivability of future science mission spacecraft. This paper discusses the requirements, enabling technologies, and challenges associated with dynamically reconfigurable space communications systems.

Future science missions will require the use of multiple spacecraft with multiple sensor nodes autonomously responding and adapting to a dynamically changing space environment. The acquisition of random scientific events will require rapidly changing network topologies, distributed processing power, and a dynamic resource management strategy. Optimum utilization and configuration of spacecraft communications and navigation resources will be critical in meeting the demand of these stringent mission requirements. There are two important trends to follow with respect to NASA's (National Aeronautics and Space Administration) future scientific missions: the use of multiple satellite systems and the development of an integrated space communications network. Reconfigurable computing and communication systems may enable versatile adaptation of a spacecraft system's resources by dynamic allocation of the processor hardware to perform new operations or to maintain functionality due to malfunctions or hardware faults. Advancements in FPGA (Field Programmable Gate Array) technology make it possible to incorporate major communication and network functionalities in FPGA chips and provide the basis for a dynamically reconfigurable communication system. Advantages of higher computation speeds and accuracy are envisioned with tremendous hardware flexibility to ensure maximum survivability of future science mission spacecraft. This paper discusses the requirements, enabling technologies, and challenges associated with dynamically reconfigurable space communications systems.

In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment. This enables these devices to become an element within a reconfigurable system performing processing of high data rate streams of data. Conventionally, these devices have performed basically fixed-function processing at the input to a system. However, through the use of component-based programming models, it is possible to view these devices as general-purpose processing accelerators where the need arises within a system. A common approach to using FPGA devices in systems at present is based on the use of a dedicated driver or software proxy mechanism. The driver or proxy is responsible for controlling the flow of data between the FPGA and other elements within the system. This approach works, but often the driver or proxy requires intimate knowledge of the algorithm running within the FPGA device. As the drive toward reconfigurable computing platforms continues, the need for a standardized middleware that can be implemented and supported on all forms of processing elements increases. Through the use of such a middleware it would be possible to interface any form of processing element, including microprocessors, digital signal processors (DSPs), FPGAs and even application specific signal processors (ASSPs) and application specific integrated circuits (ASICs). The middleware would define the mechanism by which data would be transferred between processing elements and the associated signaling necessary to ensure data integrity within the system.

Boolean functions with high algebraic immunity (AI) are vital in reducing the possibility of utilizing algebraic attacks to break an encryption system. Simple algorithms exist to compute the AI of a given n-variable Boolean function, but the time required to test a large number of functions is much greater on conventional computing systems. AI was computed for all functions through n = 5 using the SRC-6. AI was also computed for n = 5 using a C algorithm. The SRC-6 performed 4.86 times faster than a conventional processor for this computation. It is believed that this is the first enumeration of all 5-variable functions with respect to AI. Monte Carlo trials were performed for n = 6, both on the SRC-6 and utilizing a C algorithm on a conventional processor. These trials provided the first known distribution of AI for 6-variable functions. Some algorithms for computing AI require a conversion between the truth table form of the function and its algebraic normal form. The first known Verilog implementation of a reduced transeunt triangle was developed for this conversion. This reduced form requires many fewer gates and has O(n) delay versus O(2) n delay for a full transeunt triangle.

Boolean functions with high algebraic immunity (AI) are vital in reducing the possibility of utilizing algebraic attacks to break an encryption system. Simple algorithms exist to compute the AI of a given n-variable Boolean function, but the time required to test a large number of functions is much greater on conventional computing systems. AI was computed for all functions through n = 5 using the SRC-6. AI was also computed for n = 5 using a C algorithm. The SRC-6 performed 4.86 times faster than a conventional processor for this computation. It is believed that this is the first enumeration of all 5-variable functions with respect to AI. Monte Carlo trials were performed for n = 6, both on the SRC-6 and utilizing a C algorithm on a conventional processor. These trials provided the first known distribution of AI for 6-variable functions. Some algorithms for computing AI require a conversion between the truth table form of the function and its algebraic normal form. The first known Verilog implementation of a reduced transeunt triangle was developed for this conversion. This reduced form requires many fewer gates and has O(n) delay versus O(2) n delay for a full transeunt triangle.

This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system, a particular kind of specialized computer, for the radar-signal processing application of generating false radar images. It documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E, building on previous work for the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of a SRC-6E solution. The result show that the SRC-6E provides no advantage until the task is made significantly complex; for this application, this was at greater than 64 range bins. This supports the hypothesis that the algorithm requires too muon initialization effort to take much advantage of the parallel processing and pipelining of toe SRC-6E. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times.

Synthesis and Partitioning for Adaptive and Reconfigurable Computing Systems (SPARCS) is a computer aided engineering environment for reconfigurable computers. SPARCS contains software implementations of a variety of methods and algorithms for various subproblems for automating the task of producing designs for multi-FPGA (Field Programmable Gate Array) based reconfigurable computers. The SPARCS system includes tools for temporal partitioning, spatial partitioning, high-level synthesis, physical design, and arbiter synthesis. This is a comprehensive report on the SPARCS project, describing various techniques developed for solving these problems. In addition, this report contains some experimental results demonstrating the effectiveness of the SPARCS tools.

The objective of the program is to develop a Memory Distribution Network (MDM) for parallel access to secondary storage (devices) for high performance computing. The secondary storage was a large page oriented memory. It was to be connected to a smaller array of electronic processors for information retrieval. We have designed and constructed a novel reconfigurable interconnection scheme that allows a 4x4 arrays of 32x32 bits page oriented optical memory be parallel accessed with five different interconnection topologies using wavelength tuning. We have also designed, fabricated and tested the MOSIS chips that would process pages of 32x32 bits information received from the large memory before transferring the processed information to the smaller array of electronic processors. The system was capable of operating at 10 MHz with a memory retrieval throughput of 10(4) Mbits/sec. We have also demonstrated the application of parallel database search on the MDN system.

The objective of the program is to develop a Memory Distribution Network (MDM) for parallel access to secondary storage (devices) for high performance computing. The secondary storage was a large page oriented memory. It was to be connected to a smaller array of electronic processors for information retrieval. We have designed and constructed a novel reconfigurable interconnection scheme that allows a 4x4 arrays of 32x32 bits page oriented optical memory be parallel accessed with five different interconnection topologies using wavelength tuning. We have also designed, fabricated and tested the MOSIS chips that would process pages of 32x32 bits information received from the large memory before transferring the processed information to the smaller array of electronic processors. The system was capable of operating at 10 MHz with a memory retrieval throughput of 10(4) Mbits/sec. We have also demonstrated the application of parallel database search on the MDN system.

The Network of Networks (NoN) model, which is a neurobiologically motivated smart algorithm co-developed by the PI, is being applied for rapid and accurate image processing of forward and side scan sonar images in turbid environments. The model is also being used as a platform for rapid distributed communications for autonomous vehicles. Both of these applications build upon unique features of the NoN for reconfigurable computing across multiple scales of organization.

Computing hardware for control, data collection, and other purposes will prove many times over crucial resources in NASA's upcoming space missions. Ability to provide these resources within mission payload requirements, with the hardiness to operate for extended periods under potentially harsh conditions in off-World environments, is daunting enough without considering the possibility of doing so with conventional electronics. This paper examines some ideas and options, and proposes some initial approaches, for logical design of reconfigurable computing resources offering true modularity, universal compatibility, and unprecedented flexibility to service all forms and needs of mission infrastructure.

Single-photon-counting laser altimetry is a new measurement technique offering significant advantages in vertical resolution, reducing instrument size, mass, and power, and reducing laser complexity as compared to analog or threshold detection laser altimetry techniques. However, these improvements come at the cost of a dramatically increased requirement for onboard real-time data processing. Reconfigurable computing has been shown to offer considerable performance advantages in performing this processing. These advantages have been demonstrated on the Multi-KiloHertz Micro-Laser Altimeter (MMLA), an aircraft based single-photon-counting laser altimeter developed by NASA Goddard Space Flight Center with several potential spaceflight applications. This paper describes how reconfigurable computing technology was employed to perform MMLA data processing in real-time under realistic operating constraints, along with the results observed. This paper also expands on these prior results to identify concepts for using reconfigurable computing to enable spaceflight single-photon-counting laser altimeter instruments.

NASA s Constellation Program is developing a lunar surface outpost in which reconfigurable computing will play a significant role. Reconfigurable systems provide a number of benefits over conventional software-based implementations including performance and power efficiency, while the use of standardized reconfigurable hardware provides opportunities to reduce logistical overhead. The current vision for the lunar surface architecture includes habitation, mobility, and communications systems, each of which greatly benefit from reconfigurable hardware in applications including video processing, natural feature recognition, data formatting, IP offload processing, and embedded control systems. In deploying reprogrammable hardware, considerations similar to those of software systems must be managed. There needs to be a mechanism for discovery enabling applications to locate and utilize the available resources. Also, application interfaces are needed to provide for both configuring the resources as well as transferring data between the application and the reconfigurable hardware. Each of these topics are explored in the context of deploying reconfigurable resources as an integral aspect of the lunar exploration architecture.

Parallel computing systems with thousands of processors are now common and more affordable due to the focus on clustered commodity processors. However, both market and physical factors are converging that will limit the performance of these systems in the future. Hardware advances over the past several decades have been empirically observed with remarkable precision to obey Moore's law, predicting an increase in transistor density by about a factor of two every eighteen months. Maintaining these improvements has become problematic as power dissipation and other size-limiting factors become more pronounced at smaller feature size. Reconfigurable computing or heterogeneous computing, is offering hope to the scientific computing community as a way to provide continued growth in computing capability. This paper discusses some of the hardware and software associated with this new technology. It also provides a discussion on the overall state of the technology for use by computational scientists. This is done by exploring a sample problem related to bit- and integer-based applications.

The objective of the Quorum Program was to understand the basic principle and algorithms of middleware systems for Quality of Service-aware (QoS-aware) and survivable information systems. The EPIQ project aimed to develop a metacomputing framework for scalable, responsive, and reconfigurable end-to-end resource management. This meta-computing framework develops end-to-end QoS and resource management strategies that can be customized and integrated to provide guaranteed services of negotiated quality to time-critical C3I applications. Specifically, the framework provides end-to-end QoS and resource management to flexible applications and enables applications to adapt their quality if dynamic changes occur in requirements, demand on resources, and availability of resources. EPIQ multi-dimensional QoS and resource management mechanisms are application-independent, but permit integration with application-specific and user-oriented mechanisms, and give the user a crucial control in QoS, service and resource allocation adaptation, graceful degradation, and recovery. The QoS management and resource management framework is further expanded through off-line QoS programming and compilation environments to allow easy development of flexible multimedia applications within the framework. The framework validation is done through an open real-time, run-time environment that provides end-to-end, real-time performance computing and communication support for hard-real-time applications as well as end-to-end soft performance guarantees for soft real-time and flexible applications. (7 figures)

A hybrid-computing architecture consisting of a general purpose digital signal processor (DSP) closely coupled to a field-programmable gate array serving as a reconfigurable processor has been demonstrated as having great utility to collect, process, and report data from a sensor node containing acoustic and possibly other sensors. The computing architecture for microsensors (CA(mu)S) was developed jointly by ARL and Sanders tinder the auspices of the Advanced Sensors FedLab Program. CA(mu)S was used to replace an existing PCI-based computer chassis in a data collection system restilting in a ten thousand-fold improvement in size x weight x power product. The processing load is split between the general purpose DSP and the reconfigurable processor to achieve these improved results. Although in this incarnation, reconfiguration on the fly was not implemented, this paper will discuss situations where this would be advantageous. The direction of reconfigurable computing for the near future will be outlined, especially with processing acoustic signals in an array of distributed sensors.

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We describe Janus, a massively parallel FPGA-based computer optimized for the simulation of spin glasses, theoretical models for the behavior of glassy materials. FPGAs (as compared to GPUs or many-core processors) provide a complementary approach to massively parallel computing. In particular, our model problem is formulated in terms of binary variables, and floating-point operations can be (almost) completely avoided. The FPGA architecture allows us to run many independent threads with almost no latencies in memory access, thus updating up to 1024 spins per cycle. We describe Janus in detail and we summarize the physics results obtained in four years of operation of this machine; we discuss two types of physics applications: long simulations on very large systems (which try to mimic and provide understanding about the experimental non-equilibrium dynamics), and low-temperature equilibrium simulations using an artificial parallel tempering dynamics. The time scale of our non-equilibrium simulations spans eleven orders of magnitude (from picoseconds to a tenth of a second). On the other hand, our equilibrium simulations are unprecedented both because of the low temperatures reached and for the large systems that we have brought to equilibrium. A finite-time scaling ansatz emerges from the detailed comparison of the two sets of simulations. Janus has made it possible to perform spin-glass simulations that would take several decades on more conventional architectures. The paper ends with an assessment of the potential of possible future versions of the Janus architecture, based on state-of-the-art technology.

The Multi-KiloHertz Micro-Laser Altimeter (MMLA) is an aircraft based instrument developed by NASA Goddard Space Flight Center with several potential spaceflight applications. This presentation describes how reconfigurable computing technology was employed to perform MMLA signal extraction in real-time under realistic operating constraints. The MMLA is a "single-photon-counting" airborne laser altimeter that is used to measure land surface features such as topography and vegetation canopy height. This instrument has to date flown a number of times aboard the NASA P3 aircraft acquiring data at a number of sites in the Mid-Atlantic region. This instrument pulses a relatively low-powered laser at a very high rate (10 kHz) and then measures the time-of-flight of discrete returns from the target surface. The instrument then bins these measurements into a two-dimensional array (vertical height vs. horizontal ground track) and selects the most likely signal path through the array. Return data that does not correspond to the selected signal path are classified as noise returns and are then discarded. The MMLA signal extraction algorithm is very compute intensive in that a score must be computed for every possible path through the two dimensional array in order to select the most likely signal path. Given a typical array size with 50 x 6, up to 33 arrays must be processed per second. And for each of these arrays, roughly 12,000 individual paths must be scored. Furthermore, the number of paths increases exponentially with the horizontal size of the array, and linearly with the vertical size. Yet, increasing the horizontal and vertical sizes of the array offer science advantages such as improved range, resolution, and noise rejection. Due to the volume of return data and the compute intensive signal extraction algorithm, the existing PC-based MMLA data system has been unable to perform signal extraction in real-time unless the array is limited in size to one column, This limits the ability of the MMLA to operate in environments with sparse signal returns and a high number of noise return. However, under an IR&D project, an FPGA-based, reconfigurable computing data system has been developed that has been demonstrated to perform real-time signal extraction under realistic operating constraints. This reconfigurable data system is based on the commercially available Firebird Board from Annapolis Microsystems. This PCI board consists of a Xilinx Virtex 2000E FPGA along with 36 MB of SRAM arranged in five separately addressable banks. This board is housed in a rackmount PC with dual 850MHz Pentium processors running the Windows 2000 operating system. This data system performs all signal extraction in hardware on the Firebird, but also runs the existing "software based" signal extraction in tandem for comparison purposes. Using a relatively small amount of the Virtex XCV2000E resources, the reconfigurable data system has demonstrated to improve performance improvement over the existing software based data system by an order of magnitude. Performance could be further improved by employing parallelism. Ground testing and a preliminary engineering test flight aboard the NASA P3 has been performed, during which the reconfigurable data system has been demonstrated to match the results of the existing data system.

For many years researchers have tried to use reconfigurable computing technology (namely FPGAs) to help solve many computationally demands problems in domains like scientific computing, finance, security and military applications. Significant problems had to be overcome ranging from non-ideal vendor architectures with limited support for dynamic reconfigurations to a lack of programming language abstractions and tools needed to make this technology accessible to mainstream programmers. This sessions draws together speakers that will report the current state of the art in reconfigurable computing and show how computationally challenging problems involving databases, financial computing and network intrusion can now be effectively solved by the special processing capabilities of FPGAs and we also predict the future impact of this technology on mainstream software industry and identify some of the new research challenges in this field. ©2011 Microsoft Corporation. All rights reserved.

For many years researchers have tried to use reconfigurable computing technology (namely FPGAs) to help solve many computationally demands problems in domains like scientific computing, finance, security and military applications. Significant problems had to be overcome ranging from non-ideal vendor architectures with limited support for dynamic reconfigurations to a lack of programming language abstractions and tools needed to make this technology accessible to mainstream programmers. This sessions draws together speakers that will report the current state of the art in reconfigurable computing and show how computationally challenging problems involving databases, financial computing and network intrusion can now be effectively solved by the special processing capabilities of FPGAs and we also predict the future impact of this technology on mainstream software industry and identify some of the new research challenges in this field. ©2011 Microsoft Corporation. All rights reserved.

This is a fully functional model for a reconfigurable analog computing 'cell', capable of performing addition, subtraction, integration, and differentiation. The design uses 6 SPST switches, a capacitor, a few resistors, and an op-amp. The file requires Scilab's Xcos (an open source alternative to MATLAB's Simulink) in order to run. Note: Although logic gates are used to provide the switching logic for selecting the desired function, they can easily be replaced with a shift register powered by an Arduino or other Microcontroller, FPGA/CPLD, etc.

Emulation techniques are proposed as a solution to a difficulty arising in the analysis of the reliability of highly reliable computer systems for future commercial aircraft. The difficulty, viz., the lack of credible precision in reliability estimates obtained by analytical modeling techniques are established. The difficulty is shown to be an unavoidable consequence of: (1) a high reliability requirement so demanding as to make system evaluation by use testing infeasible, (2) a complex system design technique, fault tolerance, (3) system reliability dominated by errors due to flaws in the system definition, and (4) elaborate analytical modeling techniques whose precision outputs are quite sensitive to errors of approximation in their input data. The technique of emulation is described, indicating how its input is a simple description of the logical structure of a system and its output is the consequent behavior. The use of emulation techniques is discussed for pseudo-testing systems to evaluate bounds on the parameter values needed for the analytical techniques.

The focus of this project was to survey the technology of reconfigurable computing determine its level of maturity and suitability for NASA applications. To better understand and assess the effectiveness of the reconfigurable design paradigm that is utilized within the HAL-15 reconfigurable computer system. This system was made available to NASA MSFC for this purpose, from Star Bridge Systems, Inc. To implement on at least one application that would benefit from the performance levels that are possible with reconfigurable hardware. It was originally proposed that experiments in fault tolerance and dynamically reconfigurability would be perform but time constraints mandated that these be pursued as future research.

Reconfigurable computing refers to the use of processors, such as Field Programmable Gate Arrays (FPGAs), that can be modified at the hardware level to take on different processing tasks. A reconfigurable computing platform describes the hardware and software base on top of which modular extensions can be created, depending on the desired application. Such reconfigurable computing platforms can take on varied designs and implementations, according to the constraints imposed and features desired by the scope of applications. This paper introduces a PC-based reconfigurable computing platform software frameworks that is flexible and extensible enough to abstract the different hardware types and functionality that different PCs may have. The requirements of the software platform, architectural issues addressed, rationale behind the decisions made, and frameworks design implemented are discussed.

FPGA-based Configurable Computing Machines (CCMs) offer powerful and flexible general-purpose computing platforms. However, development for FPGA-based designs using modern CAD tools is geared mainly toward an ASIC-like process. This is inadequate for the needs of CCM application development. This paper discusses an application framework for developing CCM-based applications beyond just the hardware configuration. This framework leverages the advantages of CCMs (availability, programmability, visibility, and controllability) to help create CCM-based applications throughout the entire development process (i.e. design, debug, and deploy). The framework itself is deployed with the final application, thus permitting dynamic circuit configurations that include data folding optimizations based on user input. The resulting system aids in creating applications that are potentially more intuitive, easier to develop, and better performing. An example application demonstrates the use of the application framework and the potential benefits.

Reconfigurable computing refers to computations done with flexible fabrics where the data path and control flow can be customized to the application. Unlike traditional computing using the fetch, execute, and store model that is highly sequential, reconfigurable computing allows developers to program their applications both spatially and temporally. This allows for potentially great speed-ups with applications that might be well-suited for such approaches. However, programming in this style requires specialized hardware and a somewhat complex design flow. This report discusses background on the topic and highlights our experiences using this technology on two target applications. It also discusses the state-of-the-art high-level language approaches that have been offered to streamline the development cycle using these technologies.

The Georgia Institute of Technology (GIT) is highly active in developing middleware standards for high performance embedded computing (HPEC), especially for DoD-relevant applications in sensor signal processing and cognitive processing. To support this research, GIT has used the funding provided by this project to purchase, install, and make operational a 104-processor, 900+ gigaflops heterogeneous Beowulf computing cluster. The system is currently in use as a test bed and simulator in support of the embedded multiprocessor software programs in which GIT participates, particularly the HPEC Software Initiative (HPEC-SI) program. A detailed list of equipment purchased is provided later in this report. This system has significantly enhanced GIT's current research capabilities and allowed us to expand our contributions to HPEC programs by enabling wore thorough experimentation demonstration and testing of emerging standards.

The next generation earth-observation satellites will have significantly increased performance requirements. New advanced compression techniques like Bit- Plane Encoding and transformation steps based on wavelets are gaining importance. However, due to the small size of the space electronics market, the availability of devices capable to implement such algorithms is decreasing. This has motivated EADS-Astrium GmbH to search new processing technologies that can be transferred in the short term to reliable commercial space technologies. The emphasis is put on reconfigurable processing, since this is the only way to reduce risks and costs and assure the proper functionality of the satellite during its whole life. The eXtreme Processing Platform is a new runtime reconfigurable processor technology, An ESA study, with the name XPP Applicability Study was already carried out to prove the feasibility of this new technology and its superiority over different architectures being offered in the market. An important part of this study was also the transfer of the architecture to a radiation-tolerant semiconductor technology. The small satellite mission BayernSAT of the Technische Universitat Munchen will serve as a demonstration of the image processing capabilities of a new reconfigurable processing technology, the XPP, integrated in a configurable processor system based on the LEON Sparc processor.

The Network of Networks (NoN) model, which is a neurobiologically motivated smart algorithm co-developed by the PI, is being applied for rapid and accurate image processing of forward and side scan sonar images in turbid environments. The model is also being used as a platform for rapid distributed communications for autonomous vehicles. Both of these applications build upon unique features of the NoN for reconfigurable computing across multiple scales of organization, and the approach has direct relevance to several enabling technologies for Future Naval Capabilities.

The Network of Networks (NoN) model, which is a neurobiologically motivated smart algorithm co-developed by the PI, is being applied for rapid and accurate image processing of forward and side scan sonar images in turbid environments. The model is also being used as a platform for rapid distributed communications for autonomous vehicles. Both of these applications build upon unique features of the NoN for reconfigurable computing across multiple scales of organization, and the approach has direct relevance to several enabling technologies for Future Naval Capabilities.

The Network of Networks (NoN) model, which is a neurobiologically motivated smart algorithm co-developed by the PI, is being applied for rapid and accurate image processing of forward and side scan sonar images in turbid environments. The model is also being used as a platform for rapid distributed communications for autonomous vehicles. Both of these applications build upon unique features of the NoN for reconfigurable computing across multiple scales of organization, and the approach has direct relevance to several enabling technologies for Future Naval Capabilities.

Described are methods and apparatus, including computer program products, for reconfigurable environmentally adaptive computing technology. An environmental signal representative of an external environmental condition is received. A processing configuration is automatically selected, based on the environmental signal, from a plurality of processing configurations. A reconfigurable processing element is reconfigured to operate according to the selected processing configuration. In some examples, the environmental condition is detected and the environmental signal is generated based on the detected condition.