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This report proposes to use generalized stochastic Petri nets (GSPN) in reliability, maintainability, and availability studies. The novelty of this modeling approach lies on the ground of the following distinctive reasons: (1) The GSPN offers a precise description of system activities and conditions while involves less complexity, comparing to other modeling techniques. Specifically, it is an inherently effective bookkeeping for conditions and activities; (2) it provides a clairvoyant insight of the key parameters that effect RMA analysis. Causes and results of events can be easily tracked by executing the GSPN; and (3) it takes the advantage of the existence of concurrency and timing of events, thus describes accurately the sequence of events.

This report proposes to use generalized stochastic Petri nets (GSPN) in reliability, maintainability, and availability studies. The novelty of this modeling approach lies on the ground of the following distinctive reasons: (1) The GSPN offers a precise description of system activities and conditions while involves less complexity, comparing to other modeling techniques. Specifically, it is an inherently effective bookkeeping for conditions and activities; (2) it provides a clairvoyant insight of the key parameters that effect RMA analysis. Causes and results of events can be easily tracked by executing the GSPN; and (3) it takes the advantage of the existence of concurrency and timing of events, thus describes accurately the sequence of events.

We present a set of programming tools (classes and functions written in C++ and based on Message Passing Interface) for fast development of generic parallel (and non-parallel) lattice simulations. They are collectively called MDP 1.2. These programming tools include classes and algorithms for matrices, random number generators, distributed lattices (with arbitrary topology), fields and parallel iterations. No previous knowledge of MPI is required in order to use them. Some applications in electromagnetism, electronics, condensed matter and lattice QCD are presented.

As the capabilities of computing machinery grow, so does the diverse variety of their applications. The feasibility of many approaches to these applications depends solely upon the existence of computing machinery capable of performing these tasks within a given time constraint. Because the majority of the available computing machinery is general purpose in nature, tasks that do not require purpose facilities, but that do require high throughput, are condemned to execution on expensive general purpose hardware. This research describes several tasks that require fast computing machinery. These tasks do not require general purpose facilities in the sense that the computing machinery used will only perform a fixed set of tasks. Some of the tasks are simple in nature, but are required to execute on very large data sets. Other tasks are computationally intensive in addition to possibly involving large data sets. Both simple and complex algorithms are considered. The discussion includes a description of the tasks. All of the above tasks are useful; however, their value is determined in part by the time required to perform them. This work discusses three architectures for performing remote sensing tasks. These architectures can execute the described tasks more quickly than conventionally available hardware.

Parallel processing of real-time dynamic systems simulation on a multiprocessor system named OSCAR is presented. In the simulation of dynamic systems, generally, the same calculation are repeated every time step. However, we cannot apply to Do-all or the Do-across techniques for parallel processing of the simulation since there exist data dependencies from the end of an iteration to the beginning of the next iteration and furthermore data-input and data-output are required every sampling time period. Therefore, parallelism inside the calculation required for a single time step, or a large basic block which consists of arithmetic assignment statements, must be used. In the proposed method, near fine grain tasks, each of which consists of one or more floating point operations, are generated to extract the parallelism from the calculation and assigned to processors by using optimal static scheduling at compile time in order to reduce large run time overhead caused by the use of near fine grain tasks. The practicality of the scheme is demonstrated on OSCAR (Optimally SCheduled Advanced multiprocessoR) which has been developed to extract advantageous features of static scheduling algorithms to the maximum extent.

One of the most serious deterrants to the development of multiple processor architectures has been the problem of providing adequate communication between the discrete processing elements. This paper examines two communications-based constraints. The first constraint is related to the physical structure of the VLSI chip. The wider the communication path the more pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more communication capacity is needed, pushing designs closer to the pin limitations of the packaging technology. The second constraint, somewhat related to the first, is the limited speed with which data can be transmitted via internal channels. Typical speeds one can achieve on a single wire are on the order of 1 Gbps. The recent development of an Optoelectronic Multiplexer may allow VLSI chips to communicate at rates up to 7 Gbps. An architecture for a parallel processing computer which takes advantage of this new capability is presented. The feasibility of a single-chip parallel-processor based on the Optoelectronic Multiplexer is examined by projecting current trends in processor speed, power, and transistor count into estimates of throughput for a multi-processor IC.

Whether it be monitoring the thermal subsystem of Space Station Freedom, or controlling the navigation of the autonomous rover on Mars, NASA missions in the 90's cannot enjoy an increased level of autonomy without the efficient use of expert systems. Merely increasing the computational speed of uniprocessors may not be able to guarantee that real time demands are met for large expert systems. Speed-up via parallel processing must be pursued alongside the optimization of sequential implementations. Prototypes of parallel expert systems have been built at universities and industrial labs in the U.S. and Japan. The state-of-the-art research in progress related to parallel execution of expert systems was surveyed. The survey is divided into three major sections: (1) multiprocessors for parallel expert systems; (2) parallel languages for symbolic computations; and (3) measurements of parallelism of expert system. Results to date indicate that the parallelism achieved for these systems is small. In order to obtain greater speed-ups, data parallelism and application parallelism must be exploited.

One of the more interesting debates of the present day centers on whether human intelligence can be simulated by computer. The author works under the premise that neurons individually are not smart at all. Rather, they are physical units which are impinged upon continuously by other matter that influences the direction of voltage shifts across the units membranes. It is only the action of a great many neurons, billions in the case of the human nervous system, that intelligent behavior emerges. What is required to understand even the simplest neural system is painstaking analysis, bit by bit, of the architecture and the physiological functioning of its various parts. The biological neural network studied, the vestibular utricular and saccular maculas of the inner ear, are among the most simple of the mammalian neural networks to understand and model. While there is still a long way to go to understand even this most simple neural network in sufficient detail for extrapolation to computers and robots, a start was made. Moreover, the insights obtained and the technologies developed help advance the understanding of the more complex neural networks that underlie human intelligence.

Whether it be monitoring the thermal subsystem of Space Station Freedom, or controlling the navigation of the autonomous rover on Mars, NASA missions in the 1990s cannot enjoy an increased level of autonomy without the efficient implementation of expert systems. Merely increasing the computational speed of uniprocessors may not be able to guarantee that real-time demands are met for larger systems. Speedup via parallel processing must be pursued alongside the optimization of sequential implementations. Prototypes of parallel expert systems have been built at universities and industrial laboratories in the U.S. and Japan. The state-of-the-art research in progress related to parallel execution of expert systems is surveyed. The survey discusses multiprocessors for expert systems, parallel languages for symbolic computations, and mapping expert systems to multiprocessors. Results to date indicate that the parallelism achieved for these systems is small. The main reasons are (1) the body of knowledge applicable in any given situation and the amount of computation executed by each rule firing are small, (2) dividing the problem solving process into relatively independent partitions is difficult, and (3) implementation decisions that enable expert systems to be incrementally refined hamper compile-time optimization. In order to obtain greater speedups, data parallelism and application parallelism must be exploited.

The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

Computer vision systems employ a sequence of vision algorithms in which the output of an algorithm is the input of the next algorithm in the sequence. Algorithms that constitute such systems exhibit vastly different computational characteristics, and therefore, require different data decomposition techniques and efficient load balancing techniques for parallel implementation. However, since the input data for a task is produced as the output data of the previous task, this information can be exploited to perform knowledge based data decomposition and load balancing. Presented here are algorithms for a motion estimation system. The motion estimation is based on the point correspondence between the involved images which are a sequence of stereo image pairs. Researchers propose algorithms to obtain point correspondences by matching feature points among stereo image pairs at any two consecutive time instants. Furthermore, the proposed algorithms employ non-iterative procedures, which results in saving considerable amounts of computation time. The system consists of the following steps: (1) extraction of features; (2) stereo match of images in one time instant; (3) time match of images from consecutive time instants; (4) stereo match to compute final unambiguous points; and (5) computation of motion parameters.

The use of networked terminals which utilize embedded processing techniques results in totally integrated, flexible, high speed, reliable, and scalable systems suitable for telemetry and data processing applications such as mission operations centers (MOC). Synergies of these terminals, coupled with the capability of terminal to receive incoming data, allow the viewing of any defined display by any terminal from the start of data acquisition. There is no single point of failure (other than with network input) such as exists with configurations where all input data goes through a single front end processor and then to a serial string of workstations. Missions dedicated to NASA's ozone measurements program utilize the methodologies which are discussed, and result in a multimission configuration of low cost, scalable hardware and software which can be run by one flight operations team with low risk.

The use of networked terminals which utilize embedded processing techniques results in totally integrated, flexible, high speed, reliable, and scalable systems suitable for telemetry and data processing applications such as mission operations centers (MOC). Synergies of these terminals, coupled with the capability of terminal to receive incoming data, allow the viewing of any defined display by any terminal from the start of data acquisition. There is no single point of failure (other than with network input) such as exists with configurations where all input data goes through a single front end processor and then to a serial string of workstations. Missions dedicated to NASA's ozone measurements program utilize the methodologies which are discussed, and result in a multimission configuration of low cost, scalable hardware and software which can be run by one flight operations team with low risk.

The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

A capability consisting of software development and experimental techniques has been developed and is described. The capability is integrated into GENOA-PFA to model polymer matrix composite (PMC) structures. The capability considers the physics and mechanics of composite materials and structure by integration of a hierarchical multilevel macro-scale (lamina, laminate, and structure) and micro scale (fiber, matrix, and interface) simulation analyses. The modeling involves (1) ply layering methodology utilizing FEM elements with through-the-thickness representation, (2) simulation of effects of material defects and conditions (e.g., voids, fiber waviness, and residual stress) on global static and cyclic fatigue strengths, (3) including material nonlinearities (by updating properties periodically) and geometrical nonlinearities (by Lagrangian updating), (4) simulating crack initiation. and growth to failure under static, cyclic, creep, and impact loads. (5) progressive fracture analysis to determine durability and damage tolerance. (6) identifying the percent contribution of various possible composite failure modes involved in critical damage events. and (7) determining sensitivities of failure modes to design parameters (e.g., fiber volume fraction, ply thickness, fiber orientation. and adhesive-bond thickness). GENOA-PFA progressive failure analysis is now ready for use to investigate the effects on structural responses to PMC material degradation from damage induced by static, cyclic (fatigue). creep, and impact loading in 2D/3D PMC structures subjected to hygrothermal environments. Its use will significantly facilitate targeting design parameter changes that will be most effective in reducing the probability of a given failure mode occurring.

This report presents a method for doing load-flow analysis of a power system by using a decomposition approach. The power system for the Space Shuttle is used as a basis to build a model for the load-flow analysis. To test the decomposition method for doing load-flow analysis, simulations were performed on power systems of 16, 25, 34, 43, 52, 61, 70, and 79 nodes. Each of the power systems was divided into subsystems and simulated under steady-state conditions. The results from these tests have been found to be as accurate as tests performed using a standard serial simulator. The division of the power systems into different subsystems was done by assigning a processor to each area. There were 13 transputers available, therefore, up to 13 different subsystems could be simulated at the same time. This report has preliminary results for a load-flow analysis using a decomposition principal. The report shows that the decomposition algorithm for load-flow analysis is well suited for parallel processing and provides increases in the speed of execution.

The demand for very high speed data processing coupled with falling hardware costs has made large-scale parallel and distributed computer systems both desirable and feasible. Two modes of parallel processing are single instruction stream-multiple data stream (SIMD) and multiple instruction stream - multiple data stream (MIMD). PASM, a partitionable SIMD/MIMD system, is a reconfigurable multimicroprocessor system being designed for image processing and pattern recognition. An important component of these systems is the interconnection network, the mechanism for communication among the computation nodes and memories. Assuring high reliability for such complex systems is a significant task. Thus, a crucial practical aspect of an interconnection network is fault tolerance. In answer to this need, the Extra Stage Cube (ESC), a fault-tolerant, multistage cube-type interconnection network, is defined. The fault tolerance of the ESC is explored for both single and multiple faults, routing tags are defined, and consideration is given to permuting data and partitioning the ESC in the presence of faults. The ESC is compared with other fault-tolerant multistage networks. Finally, reliability of the ESC and an enhanced version of it are investigated. Keywords: Theses.

Conference on parallel image processing for earth observation systems

Conference on parallel image processing for earth observation systems

Available from National Technical Information Service, Springfield, Va

http://uf.catalog.fcla.edu/uf.jsp?st=UF027817463&ix=pm&I=0&V=D&pm=1

http://uf.catalog.fcla.edu/uf.jsp?st=UF027817463&ix=pm&I=0&V=D&pm=1

The intent of this thesis is to answer the question as to whether real time battlefield visualization, once requiring high speed UNIX workstations and specialized parallel processors, can now be now performed on relatively inexpensive off the shelf components. Alternative network topologies were implemented using 10 and 100 megabit-per-second Ethernet cards under the Linux operating system on Pentium based personal computer platforms. Network throughput, processor and video performance benchmark routines were developed to assess the hardware's potential for parallel application in a distributed environment. Code was first ported to the Linux environment. Benchmark routines were then developed and tested on various machines. Dual 200 MHz Pentium Pro processor performance exceeded the dual processor 50 MHz SUN and 40 MHz SGI UNIX workstations currently used for terrain generation by a factor of 30 using a simple ray trace algorithms as a basis for comparison. The Intel Pentium Pro personal computer proved to be a capable platform for generating six to ten frame-per-second terrain simulations. However, Fast Ethernet throughput averages only 2.5 megabytes-per-second, thereby limiting the usefulness of a distributed approach designed to increase performance by dividing workload across the network.

Computer performance modeling of possibly complex computations running on highly concurrent systems is considered. Earlier works in this area either dealt with a very simple program structure or resulted in methods with exponential complexity. An efficient procedure is developed to compute the performance measures for series-parallel-reducible task systems using queueing network models. The procedure is based on the concept of hierarchical decomposition and a new operational approach. Numerical results for three test cases are presented and compared to those of simulations.

This dissertation presents unique and valuable insight into the analysis of packet-switched data communication systems. The research described in this dissertation examines performance characteristics of two types of packet-switched data communication systems. The first system to be analyzed operates in a parallel processing environment where cooperating processors independently perform assigned tasks. In this environment, the packet delay performance is dominated by queuing delays. The second type of system examined operates in a low earth orbit (LEO) satellite communications network environment. In this type of network, delay performance is affected by both queuing and propagation effects. The objectives of this research are to study the effects of queuing and propagation on the average packet delay, the number of buffers required to implement the networks that interconnect the parallel processors, and the satellite resource utilization rates. For both types of communication systems, mathematical metamodels (Agr85) are developed to capture the effects on packet delay caused by incremental changes in network dependent parameters

This report concludes phase I of the project. Two significant accomplishments are reported, the first relating to the design of heterogeneous parallel systems, and the second related to the synthesis of parallel program for the CM-5 from Thinking Machines. A methodology for design and evaluation of parallel architectures with heterogeneous components has been developed. Specifically, the communicating processes (CP) domain in Ptolemy has been used to model heterogeneous parallel hardware systems. Our first demonstration design uses the ALPS concept (Alternative Low-level Primitive Structures). Use of the CP domain is a departure from our proposal, where we had proposed to use a discrete-event model. We have determined, however, that the CP model is considerably more convenient for high-level design of heterogeneous parallel hardware. The CP domain in Ptolemy has a multi-tasking kernel managing concurrent processes. A process, or thread, is created for each computational and communications system resource in a particular design. The CP model of computation makes it easy to write and interconnect a variety of computational resources and simulate the execution of an application to evaluate the particular architectural configuration

A software development framework for parallel processing systems based on the parallel object-oriented functional computation model PROOF is evaluated. PROOF/L, a C++ based programming language with additional parallel constructs required by PROOF, is extended to include array data type and input/output features to make PROOFIL easier to use in developing software for parallel processing systems. The front-end translator from PROOF/L to the intermediate form IFl, and the back-end translators from IFl to the C languages on two different MIMD parallel machines, nCube and KSR, are developed. Our framework is evaluated by comparing it with existing software development approaches for parallel processing systems. Our framework is suitable for large-scale parallel software development because it supports the concepts of hierarchical design and shared data, and frees the software developer from considering explicit synchronization, communication, and parallelism. The software development efforts using our framework can be greatly reduced due to implicit synchronization and communication and the compactness of PROOF/L programs. The extension of PROOF/L and the integration of PROOF/L with other programming languages to utilize existing library functions written in languages such as C and FORTRAN are also discussed.

A software development framework for parallel processing systems based on the parallel object-oriented functional computation model PROOF is evaluated. PROOF/L, a C++ based programming language with additional parallel constructs required by PROOF, is extended to include array data type and input/output features to make PROOFIL easier to use in developing software for parallel processing systems. The front-end translator from PROOF/L to the intermediate form IFl, and the back-end translators from IFl to the C languages on two different MIMD parallel machines, nCube and KSR, are developed. Our framework is evaluated by comparing it with existing software development approaches for parallel processing systems. Our framework is suitable for large-scale parallel software development because it supports the concepts of hierarchical design and shared data, and frees the software developer from considering explicit synchronization, communication, and parallelism. The software development efforts using our framework can be greatly reduced due to implicit synchronization and communication and the compactness of PROOF/L programs. The extension of PROOF/L and the integration of PROOF/L with other programming languages to utilize existing library functions written in languages such as C and FORTRAN are also discussed.

Matched-field processing (MFP) localizes sources more accurately than plane-wave beamforming by employing full-wave acoustic propagation models for the cluttered ocean environment. The minimum variance distortionless response MFP (MVDR-MFP) algorithm incorporates the MVDR technique into the MFP algorithm to enhance beamforming performance. Such an adaptive MFP algorithm involves intensive computational and memory requirements due to its complex acoustic model and environmental adaptation. The real-time implementation of adaptive MFP algorithms for large surveillance areas presents a serious computational challenge where high-performance embedded computing and parallel processing may be required to meet real-time constraints. In this paper, three parallel algorithms based on domain decomposition techniques are presented for the MVDR-MFP algorithm on distributed array systems. The parallel performance factors in terms of execution times, communication times, parallel efficiencies, and memory capacities are examined on three potential distributed systems including two types of digital signal processor arrays and a cluster of personal computers. The performance results demonstrate that these parallel algorithms provide a feasible solution for real-time, scalable, and cost-effective adaptive beamforming on embedded, distributed array systems.

Work over the three-year tenure of this grant has dealt with interrelated studies of 1) neuropharmacology, 2) behavior, and 3) distributed/ parallel processing in the generation of variable motor patterns in the buccal- oral system of the sea slug Pleurobranchaea californica. 4) Computer simulations of simple neutral networks have been undertaken to examine neurointegrative principles that could not be examined in biological preparations. The simulation work has set the basis for further simulations dealing with networks having characteristics relating to real neurons. All of the work has had the goal of developing interdisciplinary tools for understanding the 'scale-independent' problem of how individuals, each possessing only local knowledge of group activity, act within a group to produce different and variable adaptive outputs, and, in turn, of how the group influences the activity of the individual. The pharmacologic studies have had the goal of developing biochemical tools with which to identify groups of neurons that perform specific tasks during the production of a given behavior but are multifunctional by being critically involved in generating several different behaviors.

An example of the calculation of mixing flows in a solution crystal growth system is shown here. Solution crystal growth is an important means of producing a wide variety of organic and inorganic crystals. In these systems, a single crystal is grown from a supersaturated solution in which the material to be crystallized is dissolved as a solute. Macroscopic transport of solute molecules from the liquid solution phase to the faces of the growing crystal is almost wholly determined by fluid mechanics. Until recently, the extreme challenges posed by modeling flows within the 3D geometry of such systems has limited progress in understanding transport effects; the calculations shown here represent one of the first efforts to rigorously model flows within a solution crystal growth system.

A single instruction stream - multiple data stream (SIMD) computer performs one algorithm (single instruction stream) on vectors of data of a control unit (CU), processing elements (PEs), and an interconnection network. The CU broadcasts instructions to the N Pes (where N is a power of two). The interconnection network is the mechanism that allows PEs to pass data among themselves. Four types of interconnection networks are discussed in this work: the Shuffle-Exchange network, the Cube network, the ILLIAC network, and the Plus-Minus 2 (PM2I) network. Each type has been discussed in the literature and used in an existing or proposed machine design. For each of these four network types, different hardware structures are considered. A recirculating network consists of one stage of switches that is reused until the data reach their final destinations. A combinational logic multistage network consists of several stages of switches and, usually, data is transferred in one pass through the network. In pipelined multistage networks, which are introduced, registers are inserted after each stage of a combinational logic multistage network. The data are divided into segments, and these segments are passed in a parallel-pipelined manner. Hardware implementations for recirculating, combinational logic multistage, and pipelined multistage networks are presented and analyzed.

Continuous innovations in adaptive matched-field processing (MFP) algorithms have presented significant increases in computational complexity and resource requirements that make development and use of advanced parallel processing techniques imperative. In real-time sonar systems operating in severe underwater environments, there is a high likelihood of some part of systems exhibiting defective behavior, resulting in loss of critical network, processor, and sensor elements, and degradation in beam power pattern. Such real-time sonar systems require high reliability to overcome these challenging problems. In this paper, efficient fault-tolerant parallel algorithms based on coarse-grained domain decomposition methods are developed in order to meet real-time and reliability requirements on distributed array systems in the presence of processor and sensor element failures. The performance of the fault-tolerant parallel algorithms is experimentally analyzed in terms of beamforming performance, computation time, speedup, and parallel efficiency on a distributed testbed. The performance results demonstrate that these fault-tolerant parallel algorithms can provide real-time, scalable, lightweight, and fault-tolerant implementations for adaptive MFP algorithms on distributed array systems.

To date if has been demonstrated that an experimental animal, the sea slug Pleurobranchaea, is capable of one-trial food-aversion learning, and that the muscarinic antagonist scopolamine in low doses causes an enhancement of learning. Pharmacologic binding studies using a new, 125 sub I-form of quinuclidinyl benzilate, in addition to studies using the 3 sub H-form of this ligand, have uncovered not only the classical types of muscarinic receptors that are typical of vertebrate cortex, but also a new form that is not found in other invertebrates that we have tested. Usually muscarinic receptors are found in low densities in invertebrate neural membranes, but the density of the new form in this animal's neural membranes is similar to the density of the classic receptors in mammalian cortex. Neurophysiological studies of individual neurons in small groups of identifiable neurons have shown that their activity is variable, as is the behavior that they take part in generating, and that the variability fits the definition of low-dimensional chaos. Findings show that such variability is an important feature of the emergence of adaptive responses arising from parallel, distributed neural networks in biological systems.

In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checkpointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper Fault-Tolerant Parallel Processor (FTPP). When used in conjunction with the FTPP's fault detection and masking capabilities, this implementation results in a graceful degradation of system performance after faults. Three graceful degradation algorithms have been implemented and are presented. A user interface has been implemented which requires minimal cognitive overhead by the application programmer, masking such complexities as the system's redundancy, distributed nature, variable complement of processing resources, load balancing, fault occurrence and recovery. This user interface is described and its use demonstrated. The applicability of the functional programming style to the Activation Framework, a paradigm for intelligent systems, is then briefly described.

One of the most serious deterrants to the development of multiple processor architectures has been the problem of providing adequate communication between the discrete processing elements. This thesis examine two communications-based constraints. The first constraint is related to the physical structure of the VLSI chip. The wider the communication path the more pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more communication capacity is needed, pushing designs closer to the pin limitation of the packaging technology. The second constraint, somewhat related to the first, is the limited speed with which data can be transmitted via internal channels. Typical speeds one can achieve on a single wires are on the order of 1 Gbps. The recent development of an Optoelectronic Multiplexer may allow VLSI chips to communicate at rates up to 7 Gbps. An architecture for a parallel processing computer which takes advantage of this new capability is presented. The feasibility is presented. The feasibility of a single-chip parallel-processor based on the Optoelectronic Multiplexer is examined by projecting current trends in processor speed, power, and transistor count into estimates of throughput for a multi-processor IC.

The algorithms used in image processing are becoming longer and more complex as researchers strive to create vision systems whose performance rivals that of the human's. The size and complexity of these algorithms, however, generally do not allow them to be run in 'real time' on any sequential (Von Neumann) machine. Image processing algorithms tend to be highly parallel in nature. One can hope, therefore, that the recent advances in parallel computing will bring significant speed-ups in the execution times of image processing algorithms. However, it is usually the case that image processing systems are extremely computationally intensive. Even with speed-ups brought about by parallel computers, there is a demand for an advisory system that optimizes the execution time of image processing algorithms. A reasonable goal for such a system is as follows. Given a list of all the subtasks that need to be run for a given image processing task, produce an initial schedule and configuration and then adjust the schedule and configuration during runtime based on the current configuration and intermediate processing results. The proposed work will proceed towards this goal on several fronts. Theses.

A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.

A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.

In the sequential world, the mapping of processes to a computer system was not a problem because of the classic Von Newman architecture. However, in the parallel world, the mapping of processes to nodes and the balancing of the load on each node becomes an issue that needs to be addressed. This problem enters software development in the implementation phase and remains an issue through the testing and system integration phases. This report describes a new method developed to improve the mapping on a hypercube system. This new hypersphere mapping approach performs an optimal mapping based on the geometry of the physical system and the communication patterns of the processes. The hypersphere mapper can map processes to nodes where the number of processes exceeds the number of nodes. Other mapping approaches rely on heuristics to cluster the communication graphs into subgraphs to accomplish this mapping. The hypersphere mapper can be instrumental in the implementation phase of software development by specifying an optimal mapping that will improve the performance of the system. This method also provides a transparent programming environment, where the programmer does not need to know about the interconnection network of the physical computer system. The hypersphere mapper was tested using simulated directed and undirected random communication graphs.

A set of computer aided software engineering (CASE) tools for the software development framework for parallel processing systems based on the Parallel Object Oriented Functional computation model (PROOF) toward the automation of object oriented software development for parallel processing systems is presented. An object oriented analysis tool has been developed to identify and express parallelism in the problem statement. We have developed a communication estimation tool to estimate the communication among objects, and a clustering tool to partition the objects in groups so that the intergroup communication is reduced and concurrency with specified user requirements is realized. The parallelism analysis tool further explores potential parallelism by analyzing the invocation relations and data flow among objects. The PROOF/L back end translator is extended to support clustering and dynamic allocation features in order to achieve better performance on a workstation cluster. The software effort using our approach can be greatly reduced due to implicit synchronization and communication, the user friendly graphical interfaces of the CASE tools, the automated object oriented analysis and parallelism analysis. The performance of software developed using our approach can be improved due to the integration of the object clustering algorithm, the parallelism analysis tool and the extended back end translator.

A set of computer aided software engineering (CASE) tools for the software development framework for parallel processing systems based on the Parallel Object Oriented Functional computation model (PROOF) toward the automation of object oriented software development for parallel processing systems is presented. An object oriented analysis tool has been developed to identify and express parallelism in the problem statement. We have developed a communication estimation tool to estimate the communication among objects, and a clustering tool to partition the objects in groups so that the intergroup communication is reduced and concurrency with specified user requirements is realized. The parallelism analysis tool further explores potential parallelism by analyzing the invocation relations and data flow among objects. The PROOF/L back end translator is extended to support clustering and dynamic allocation features in order to achieve better performance on a workstation cluster. The software effort using our approach can be greatly reduced due to implicit synchronization and communication, the user friendly graphical interfaces of the CASE tools, the automated object oriented analysis and parallelism analysis. The performance of software developed using our approach can be improved due to the integration of the object clustering algorithm, the parallelism analysis tool and the extended back end translator.

The intent of this thesis is to answer the question as to whether real time battlefield visualization, once requiring high speed UNIX workstations and specialized parallel processors, can now be now performed on relatively inexpensive off the shelf components. Alternative network topologies were implemented using 10 and 100 megabit-per-second Ethernet cards under the Linux operating system on Pentium based personal computer platforms. Network throughput, processor and video performance benchmark routines were developed to assess the hardware's potential for parallel application in a distributed environment. Code was first ported to the Linux environment. Benchmark routines were then developed and tested on various machines. Dual 200 MHz Pentium Pro processor performance exceeded the dual processor 50 MHz SUN and 40 MHz SGI UNIX workstations currently used for terrain generation by a factor of 30 using a simple ray trace algorithms as a basis for comparison. The Intel Pentium Pro personal computer proved to be a capable platform for generating six to ten frame-per-second terrain simulations. However, Fast Ethernet throughput averages only 2.5 megabytes-per-second, thereby limiting the usefulness of a distributed approach designed to increase performance by dividing workload across the network.

The intent of this thesis is to answer the question as to whether real time battlefield visualization, once requiring high speed UNIX workstations and specialized parallel processors, can now be now performed on relatively inexpensive off the shelf components. Alternative network topologies were implemented using 10 and 100 megabit-per-second Ethernet cards under the Linux operating system on Pentium based personal computer platforms. Network throughput, processor and video performance benchmark routines were developed to assess the hardware's potential for parallel application in a distributed environment. Code was first ported to the Linux environment. Benchmark routines were then developed and tested on various machines. Dual 200 MHz Pentium Pro processor performance exceeded the dual processor 50 MHz SUN and 40 MHz SGI UNIX workstations currently used for terrain generation by a factor of 30 using a simple ray trace algorithms as a basis for comparison. The Intel Pentium Pro personal computer proved to be a capable platform for generating six to ten frame-per-second terrain simulations. However, Fast Ethernet throughput averages only 2.5 megabytes-per-second, thereby limiting the usefulness of a distributed approach designed to increase performance by dividing workload across the network.