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Reproducibility review completed, adding a registration for proper archival and snapshot.

Reproducibility review completed, adding a registration for proper archival and snapshot.

Being one of the most elegant sensory organs of the human body, anomalies in the retina can have serious consequences on the vision system and are indicative of specific medical conditions. Off the shelf fundus cameras are capable of acquiring high quality retinal images, yet accurate interpretation of retinal images remains a major bottleneck in the early detection of asymptomatic retinal conditions. Decades of research has led to numerous retinal image segmentation algorithms which can map blood vessels in retina images, and identify some of the most telling retina lesions. Despite this significant progress, how to derive personalized optimal parameters for automated mapping remains an open issue. In this talk, I will discuss our recent work in personalized modeling of blood vessel mapping algorithms. The technique is based on statistical fitting of selective image features to a statistical distribution, using a Sobel (or similar) edge detector as a “probe” to measure the personalized optimal threshold parameter for BV mapping. The approach allows systematic tradeoff analysis between detection sensitivity and false detection rates. The implementation of these mapping algorithms on a Pico FPGA card on a laptop achieves 30x acceleration over a CPU based implementation. We plan to utilize the very high level of parallelism offered by FPGA cluster/FPGA cards to extract region-based features for cloud-level image indexing/retrieval applications, and client crowd-based image feature processing and aggregation. ©2011 Microsoft Corporation. All rights reserved.

Being one of the most elegant sensory organs of the human body, anomalies in the retina can have serious consequences on the vision system and are indicative of specific medical conditions. Off the shelf fundus cameras are capable of acquiring high quality retinal images, yet accurate interpretation of retinal images remains a major bottleneck in the early detection of asymptomatic retinal conditions. Decades of research has led to numerous retinal image segmentation algorithms which can map blood vessels in retina images, and identify some of the most telling retina lesions. Despite this significant progress, how to derive personalized optimal parameters for automated mapping remains an open issue. In this talk, I will discuss our recent work in personalized modeling of blood vessel mapping algorithms. The technique is based on statistical fitting of selective image features to a statistical distribution, using a Sobel (or similar) edge detector as a “probe” to measure the personalized optimal threshold parameter for BV mapping. The approach allows systematic tradeoff analysis between detection sensitivity and false detection rates. The implementation of these mapping algorithms on a Pico FPGA card on a laptop achieves 30x acceleration over a CPU based implementation. We plan to utilize the very high level of parallelism offered by FPGA cluster/FPGA cards to extract region-based features for cloud-level image indexing/retrieval applications, and client crowd-based image feature processing and aggregation. ©2011 Microsoft Corporation. All rights reserved.

This presentation provides information on the progress the Intelligent Payload Module (IPM) development effort. In addition, a vision is presented on integration of the IPM architecture with the GeoSocial Application Program Interface (API) architecture to enable efficient distribution of satellite data products.

This presentation provides information on the progress the Intelligent Payload Module (IPM) development effort. In addition, a vision is presented on integration of the IPM architecture with the GeoSocial Application Program Interface (API) architecture to enable efficient distribution of satellite data products.

In this paper we introduce and investigate the statistical mechanics of hierarchical neural networks: First, we approach these systems \`a la Mattis, by thinking at the Dyson model as a single-pattern hierarchical neural network and we discuss the stability of different retrievable states as predicted by the related self-consistencies obtained from a mean-field bound and from a bound that bypasses the mean-field limitation. The latter is worked out by properly reabsorbing fluctuations of the magnetization related to higher levels of the hierarchy into effective fields for the lower levels. Remarkably, mixing Amit's ansatz technique (to select candidate retrievable states) with the interpolation procedure (to solve for the free energy of these states) we prove that (due to gauge symmetry) the Dyson model accomplishes both serial and parallel processing. One step forward, we extend this scenario toward multiple stored patterns by implementing the Hebb prescription for learning within the couplings. This results in an Hopfield-like networks constrained on a hierarchical topology, for which, restricting to the low storage regime (where the number of patterns grows at most logarithmical with the amount of neurons), we prove the existence of the thermodynamic limit for the free energy and we give an explicit expression of its mean field bound and of the related improved bound

How do we assign nouns correctly to their underlying case roles in English, and how do we select an appropriate verb frame to assign these nouns to? How do we know whether a noun phrase is a modifier of a preceding noun phrase or an argument of the verb? How do we select the correct meaning of each noun in the sentence, and how do we allow content to modulate its meaning? How do we know how to handle these new nouns and verbs? In this article we describe a simulation model that addresses these questions from a perspective quite different from the conventional perspective found in Computational Linguistics. Words are treated as patterns of activation, and knowledge about them is stored in distributed form, in the connections in a large network of simple neutron-like processing units. The model exhibits considerable facility in dealing with the problems of frame selection, role assignment, disambiguation, etc, and suggests a natural way to resolve unappealing aspects of the idea that there is a fixed set of individuated case roles. So far, our simulation model can only process one clause sentences. Possible extensions to multi-clause sentences are described.

Includes bibliographical references and index

VMS RTL Parallel Processing Manual

VMS RTL Parallel Processing Manual

VMS RTL Parallel Processing Manual

This work presents a novel method for detecting straight lines in an image at a very high speed with optimum number of processors and their functionalities. The method can be used to extract straight lines directly from an image without noise removal and pre-processing. First the square image is converted to a binary edge image using a parallel edge detection mechanism. The parallel edge detection mechanism used in this work is capable of producing edge image within a short time. Then the binary square image is transferred to a system having large number of Processing Elements (PEs). A PE has only limited jobs such as pixel scanning, compare line length with nearby PEs and transmit data to the Main Control Unit (MCU). The MCU collects data from all PEs and evaluates straight lines. Even if the number of PEs is high, it is comparatively very much less than the parallel Hough Transform method and practically implementable using recent ULSI technologies. 

Whether it be monitoring the thermal subsystem of Space Station Freedom, or controlling the navigation of the autonomous rover on Mars, NASA missions in the 1990s cannot enjoy an increased level of autonomy without the efficient implementation of expert systems. Merely increasing the computational speed of uniprocessors may not be able to guarantee that real-time demands are met for larger systems. Speedup via parallel processing must be pursued alongside the optimization of sequential implementations. Prototypes of parallel expert systems have been built at universities and industrial laboratories in the U.S. and Japan. The state-of-the-art research in progress related to parallel execution of expert systems is surveyed. The survey discusses multiprocessors for expert systems, parallel languages for symbolic computations, and mapping expert systems to multiprocessors. Results to date indicate that the parallelism achieved for these systems is small. The main reasons are (1) the body of knowledge applicable in any given situation and the amount of computation executed by each rule firing are small, (2) dividing the problem solving process into relatively independent partitions is difficult, and (3) implementation decisions that enable expert systems to be incrementally refined hamper compile-time optimization. In order to obtain greater speedups, data parallelism and application parallelism must be exploited.

As the integration of VLSI systems becomes larger and denser, implementing a high-performance parallel architecture using a global clock is becoming more inefficient and difficult to design, primarily due to concerns related to clock skew and data synchronization. To solve this problem, a large system may be broken up into asynchronously communicating processors. Each processor can be either asynchronous or synchronous and therefore execute at a rate best suited for individual tasks. Using such asynchronous communication provides a modular design environment in which processors can be individually optimized to yield prominent performance improvement. However the advantages of asynchronous design do not come without a cost, due to two-way communication and design restrictions necessary to avoid hazards and races. In addition, adopting an asynchronous design style requires new methods for synthesis and verification. This research work addressed these methods to simplify the design methodology for asynchronous processors and improve their performance. To provide similar easy-to-use synthesis tools for the design of asynchronous systems, as are available and widely used in the design of synchronous systems, we have developed CAD tools that allow automated design of synchronous, asynchronous, and mixed synchronous/ asynchronous circuits. Our work can be summarized in three major topics: automated gate-level synthesis of asynchronous circuits, a uniform approach to both synchronous and asynchronous circuit synthesis, and efficient verification.

The application was divided into two experiments. In the first we proposed to examine the development of topographical connections from the olfactory mucosa to the olfactory bulb, using microinjections of HRP. The bulk of the equipment purchased with ONR money was designed to perform these experiments. Due to a long chain of mix-ups and delays, the equipment did not arrive in Charlottesville until nearly 8 months after the start of the grant. While waiting to begin the first group of experiments, we concentrated our efforts on Experiment 2 and on completing other studies relevant to understanding the development of bulb circuitry.

Track reconstruction in high track multiplicity environments at current and future high rate particle physics experiments is a big challenge and very time consuming. The search for track seeds and the fitting of track candidates are usually the most time consuming steps in the track reconstruction. Here, a new and fast track reconstruction method based on hit triplets is proposed which exploits a three-dimensional fit model including multiple scattering and hit uncertainties from the very start, including the search for track seeds. The hit triplet based reconstruction method assumes a homogeneous magnetic field which allows to give an analytical solutions for the triplet fit result. This method is highly parallelizable, needs fewer operations than other standard track reconstruction methods and is therefore ideal for the implementation on parallel computing architectures. The proposed track reconstruction algorithm has been studied in the context of the Mu3e-experiment and a typical LHC experiment.

A discussion on parallel processing approaches for Linux. Home Page .

We study the problem of computing a conjunctive query q in parallel, using p of servers, on a large database. We consider algorithms with one round of communication, and study the complexity of the communication. We are especially interested in the case where the data is skewed, which is a major challenge for scalable parallel query processing. We establish a tight connection between the fractional edge packings of the query and the amount of communication, in two cases. First, in the case when the only statistics on the database are the cardinalities of the input relations, and the data is skew-free, we provide matching upper and lower bounds (up to a poly log p factor) expressed in terms of fractional edge packings of the query q. Second, in the case when the relations are skewed and the heavy hitters and their frequencies are known, we provide upper and lower bounds (up to a poly log p factor) expressed in terms of packings of residual queries obtained by specializing the query to a heavy hitter. All our lower bounds are expressed in the strongest form, as number of bits needed to be communicated between processors with unlimited computational power. Our results generalizes some prior results on uniform databases (where each relation is a matching) [4], and other lower bounds for the MapReduce model [1].

This project explored the workform model of parallel processing, looking at its implications for parallel architectures, operating systems and parallel application structuring. The architecture investigation lead to the design and construction of a scalable shared memory multiprocessor, ParaDiGM, that included as novel features: large cache lines, software-controlled caches, locking and messaging support in the caches and hierarchically shared caches. Various detailed studies coming from this work has shown that these features provide major improvements in cost-effective scalability for parallel computation, particularly parallel simulations. The work on parallel operating system support lead to two major innovations, application-controlled page caches and memory-based messaging. The former allows an application to completely control the allocation of physical memory allocated to it, avoiding unexpected page faults. The latter provides application-level access to the hardware- supported memory-based messaging as well as providing an extended abstraction of this facility.

This project explored the workform model of parallel processing, looking at its implications for parallel architectures, operating systems and parallel application structuring. The architecture investigation lead to the design and construction of a scalable shared memory multiprocessor, ParaDiGM, that included as novel features: large cache lines, software-controlled caches, locking and messaging support in the caches and hierarchically shared caches. Various detailed studies coming from this work has shown that these features provide major improvements in cost-effective scalability for parallel computation, particularly parallel simulations. The work on parallel operating system support lead to two major innovations, application-controlled page caches and memory-based messaging. The former allows an application to completely control the allocation of physical memory allocated to it, avoiding unexpected page faults. The latter provides application-level access to the hardware- supported memory-based messaging as well as providing an extended abstraction of this facility.

This project explored the workform model of parallel processing, looking at its implications for parallel architectures, operating systems and parallel application structuring. The architecture investigation lead to the design and construction of a scalable shared memory multiprocessor, ParaDiGM, that included as novel features: large cache lines, software-controlled caches, locking and messaging support in the caches and hierarchically shared caches. Various detailed studies coming from this work has shown that these features provide major improvements in cost-effective scalability for parallel computation, particularly parallel simulations. The work on parallel operating system support lead to two major innovations, application-controlled page caches and memory-based messaging. The former allows an application to completely control the allocation of physical memory allocated to it, avoiding unexpected page faults. The latter provides application-level access to the hardware- supported memory-based messaging as well as providing an extended abstraction of this facility.

This project explored the workform model of parallel processing, looking at its implications for parallel architectures, operating systems and parallel application structuring. The architecture investigation lead to the design and construction of a scalable shared memory multiprocessor, ParaDiGM, that included as novel features: large cache lines, software-controlled caches, locking and messaging support in the caches and hierarchically shared caches. Various detailed studies coming from this work has shown that these features provide major improvements in cost-effective scalability for parallel computation, particularly parallel simulations. The work on parallel operating system support lead to two major innovations, application-controlled page caches and memory-based messaging. The former allows an application to completely control the allocation of physical memory allocated to it, avoiding unexpected page faults. The latter provides application-level access to the hardware- supported memory-based messaging as well as providing an extended abstraction of this facility.

This project explored the workform model of parallel processing, looking at its implications for parallel architectures, operating systems and parallel application structuring. The architecture investigation lead to the design and construction of a scalable shared memory multiprocessor, ParaDiGM, that included as novel features: large cache lines, software-controlled caches, locking and messaging support in the caches and hierarchically shared caches. Various detailed studies coming from this work has shown that these features provide major improvements in cost-effective scalability for parallel computation, particularly parallel simulations. The work on parallel operating system support lead to two major innovations, application-controlled page caches and memory-based messaging. The former allows an application to completely control the allocation of physical memory allocated to it, avoiding unexpected page faults. The latter provides application-level access to the hardware- supported memory-based messaging as well as providing an extended abstraction of this facility.

The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

The application of Predictor corrector integration algorithms developed for the digital parallel processing environment are investigated. The algorithms are implemented and evaluated through the use of a software simulator which provides an approximate representation of the parallel processing hardware. Test cases which focus on the use of the algorithms are presented and a specific application using a linear model of a turbofan engine is considered. Results are presented showing the effects of integration step size and the number of processors on simulation accuracy. Real time performance, interprocessor communication, and algorithm startup are also discussed.

Distributed Array Processors (DAP) have been in day to day use for ten years and a large amount of user experience has been gained. The profile of user applications is similar to that of the Massively Parallel Processor (MPP) working group. Experience has shown that contrary to expectations, highly parallel systems provide excellent performance on so-called dirty problems such as the physics part of meteorological codes. The reasons for this observation are discussed. The arguments against replacing bit processors with floating point processors are also discussed.

Parafrase transforms a FORTRAN code, subroutine by subroutine, into a parallel code for a vector and/or shared-memory multiprocessor system. Parafrase is not a compiler; it transforms a code and provides information for a vector or concurrent process. Parafrase uses a data dependency to reveal parallelism among instructions. The data dependency test distinguishes between recurrences and statements that can be directly vectorized or parallelized. A number of transformations are required to build a data dependency graph.

The following document reviews advances in the optoelectronic areas supported by the contract. Specifically, monolithic integration of Vertical Cavity Surface Emitting Lasers (VCSELs) arrays with Heterojunction Bipolar Transistors (HBTs) is described for the realization of smart pixels. Latching, non-latching and bistable switching is demonstrated for the arrays. In addition, it is shown that the arrays can perform cascadable Boolean logic. Further, low series resistance and high speed(> 9 GHz) VCSELs were realized while maintaining average output powers of 2-5 mW. Pico-second pulse generation in diode lasers-both edge emitters and VCSELs is reported, and regenerative mode locking is described for both types of device. Optical pumping of RPG-VCSEL structures is described, and the approaches to phase coupled VCSEL arrays is enumerated. Finally, preliminary experiments and models aimed at the understanding of dynamic behavior in VCSELs are presented.

The numerical solution of many problems in continuum dynamics is seriously limited by the computation rates attainable on computers with serial architecture. Parallel processing machines can achieve much higher rates. However, applying additional processors to a calculation is only part of the solution. In this report, parallel algorithms are developed for explicit and implicit, Lagrangian and Eulerian finite difference schemes for computational continuum dynamics in one spatial dimension. First, the explicit conservation equations in the Lagrangian reference frame are readily reformulated for concurrent processing. Second, and implicit solution is derived for these equations. This is important because it yields unconditional stability. The parallelism is achieved via a block implicit numerical scheme. Third, a rezoning algorithm is employed with each Lagrangian integration step to transform the mesh back to the Eulerian reference frame. Along the algorithmic development path, a zone-by-zone parallelization gives way to a block-by-block technique both of which are self-scheduling. Then the latter is compared to an approach that keeps the parallel processes alive for many time steps. At each step of this research exploiting the architectural advantages of the HEP H1000 (Heterogeneous Element Processor) computer. (Author)

The supervised relaxation operator combines the information from multiple ancillary data sources with the information from multispectral remote sensing image data and spatial context. Iterative calculation integrate information from the various sources, reaching a balance in consistency between these sources of information. The supervised relaxation operator is shown to produce substantial improvements in classification accuracy compared to the accuracy produced by the conventional maximum likelihood classifier using spectral data only. The convergence property of the supervised relaxation algorithm is also described. Improvement in classification accuracy by means of supervised relaxation comes at a high price in terms of computation. In order to overcome the computation-intensive problem, a distributed/parallel implementation is adopted to take advantage of a high degree of inherent parallelism in the algorithm.

Complex Helicopter Analysis codes, such as the Second Generation Comprehensive Helicopter Analysis System (2GCHAS), have been developed to provide a common framework for interdisciplinary design and analysis of rotorcraft systems. A major limitation on the effectiveness of the second generation comprehensive analysis codes is the slow processing speed that results from the computational intensity of the analysis software. The goal of phase I effort is to carefully define the specification for the parallelization opportunities in 2GCHAS, and apply the parallel processing techniques on a sample analysis to demonstrate a proof of concept. The Onyx Computer System from Silicon Graphics Inc. was chosen as the target machine for this effort as it has 4 processors and was available to ART. The tasks performed during the Phase I Base effort went beyond meeting the Phase I objectives and included the following: (1) Port of the most recent version of 2GCHAS Analysis to the Silicon Graphics Computer System. (2) Parallelize multicase analysis in 2GCHAS. (3) Choose an appropriate analysis component for parallelization in a single case analysis. (4) Parallelize Linearization Analysis and thereby reduce the overall runtime of a single case Linear System analysis. (5) Identify candidates for future parallelization in 2GCHAS. In addition, efforts had been made to improve the eigenanalysis solution method. The result obtained from the Phase I effort showed over an order of magnitude reduction in the overall runtime for the sample problems due to parallelization, better RDB implementation, less overhead in a process invocation, improved analysis algorithm and faster machine speed.

It is well known that parallel computers can be used very effectively for image processing at the pixel level, by assigning a processor to each pixel or block of pixels, and passing information as necessary between processors whose blocks are adjacent. This paper discusses the use of parallel computers for processing images at the region level, assigning a processor to each region and passing information between processors whose regions are related. The basic difference between the pixel and region levels is that the regions (e.g., obtained by segmenting the given image) and relationships differ from image to image, and even for a given image, they do not remain fixed during processing. Thus one cannot use the standard type of cellular parallelism, in which the set of processors and interprocessor connections remain fixed, for processing at the region level. Reconfigurable cellular computers, in which the set of processors that each processor can communicate with can change during a computation, are more appropriate. A class of such computers is described, and general examples are given illustrating how such a computer could initially configure itself to represent a given decomposition of an image into regions, and dynamically reconfigure itself, in parallel, as regions merge or split. (Author)

The high resolution direction of arrival (DOA) estimation has been an important area of research for a number of years. Many researchers have developed a variety of algorithms to estimate the direction of arrival. Another important aspect of the DOA estimation area is the development of high speed hardware capable of computing the DOA in real time. In this research we have first focussed on the development of parallel architecture for multiple signal classification (MUSIC) and estimation os signal parameters by rotational invariance technique (ESPRIT) algorithms for the narrow band sources. These algorithms are substituted with computationally efficient modules and converted to pipelined and parallel algorithms. For example one important computation of eigendecomposition of the covariance matrix has been performed using Householders transformations and QR method.

PSI's CAD approach to simulation/software development cuts large system life cycle costs by an order of magnitude. A visual representation of software architecture that provides a one-to-one mapping to the code, it's based upon separation data from instructions, affording separation of architecture from language, and providing ease of control and reuse of complex modules. This paradigm shift for software brakes barriers to building complex systems, makes significant upgrades easy, and cuts support costs dramatically, by achieving module independence through visually enforced architectural design rules. Its success has resulted in huge simuatlions that meet customer validity contraints but now exceed single processor computer power by one or two orders of magnitude. Hardware designers produce parallel computers with speeds into teraflop ranges. However, their practical use on all but very special problems has been extremely limited due to software implementation problems. This research is to confirm hypotheses that graphical design rules that achieve software understandability and module independence also support allocation of processes to parallel processors. Fusion of this technology with parallel processors can result in an order of magnitude of speed improvement, yet making development easier on parallel machines than single processor machines due to concurrent memory access and management.

Publish and subscribe approaches to information management systems reduce the complexity of these systems by loosely coupling publishers of information to subscribers of information through an intervening broker. Publications are typically written in Extensible Markup Language (XML) metadata, which a broker compares to XML Path Language (XPATH) predicates representing he subscriptions. Brokering matches result in the dissemination of a particular publication. Both the parsing of the American Standard Code for information interchange (ASCII) XML metadata and the evaluation of the logical predicates are time-consuming for programmable microprocessors. Augmenting programmable microprocessors with hardware acceleration from a Field Programmable Gate Array (FPGA) was determined here to reduce the latency and improved the throughput of this brokering. A hardware system was designed, built, and tested based upon utilizing (FPGA's) in the brokering process. Subscriptions were converted to hash values, and Look-Up-Table's (LUT's) were then synthesized on the FPGA's that corresponded to the hard value subscriptions. Ways to increase the reusability of LUT's were developed and demonstrated, which resulted in faster syntheses times, and an increase in the number of subscriptions possible on one FPGA. A software tool was developed and tested to completely facilitate automatic design generation for the FPGA syntheses. A method was developed and implemented to transfer multiple XML documents in group, which reduced the time delay in data transfer, the bottleneck in brokering, between the microprocessor and the FPGA. The brokering time of new publications was reduced to an average of 13 micron sec.

1 online resource (600 pages)

1 online resource (600 pages)

Featured by centralized processing and cloud based infrastructure, Cloud Radio Access Network (C-RAN) is a promising solution to achieve an unprecedented system capacity in future wireless cellular networks. The huge capacity gain mainly comes from the centralized and coordinated signal processing at the cloud server. However, full-scale coordination in a large-scale C-RAN requires the processing of very large channel matrices, leading to high computational complexity and channel estimation overhead. To resolve this challenge, we exploit the near-sparsity of large C-RAN channel matrices, and derive a unified theoretical framework for clustering and parallel processing. Based on the framework, we propose a dynamic nested clustering (DNC) algorithm that not only greatly improves the system scalability in terms of baseband-processing and channel-estimation complexity, but also is amenable to various parallel processing strategies for different data center architectures. With the proposed algorithm, we show that the computation time for the optimal linear detector is greatly reduced from $O(N^3)$ to no higher than $O(N^{\frac{42}{23}})$, where $N$ is the number of RRHs in C-RAN.

Relativistic fluid dynamics is a major component in dynamical simulations of the quark-gluon plasma created in relativistic heavy-ion collisions. Simulations of the full three-dimensional dissipative dynamics of the quark-gluon plasma with fluctuating initial conditions are computationally expensive and typically require some degree of parallelization. In this paper, we present a GPU implementation of the Kurganov-Tadmor algorithm which solves the 3+1d relativistic viscous hydrodynamics equations including the effects of both bulk and shear viscosities. We demonstrate that the resulting CUDA-based GPU code is approximately two orders of magnitude faster than the corresponding serial implementation of the Kurganov-Tadmor algorithm. We validate the code using (semi-)analytic tests such as the relativistic shock-tube and Gubser flow.

Relativistic fluid dynamics is a major component in dynamical simulations of the quark-gluon plasma created in relativistic heavy-ion collisions. Simulations of the full three-dimensional dissipative dynamics of the quark-gluon plasma with fluctuating initial conditions are computationally expensive and typically require some degree of parallelization. In this paper, we present a GPU implementation of the Kurganov-Tadmor algorithm which solves the 3+1d relativistic viscous hydrodynamics equations including the effects of both bulk and shear viscosities. We demonstrate that the resulting CUDA-based GPU code is approximately two orders of magnitude faster than the corresponding serial implementation of the Kurganov-Tadmor algorithm. We validate the code using (semi-)analytic tests such as the relativistic shock-tube and Gubser flow.

Many of today's scientific and industrial problems require enormous computing power. Since circuit switching speeds are reaching fundamental limits, avenues to speed up computations other than that using faster components are being explored. One such avenue is the use of parallelism. PASM is a dynamically reconfigurable SIMD/MIMD parallel processing system with up to 1,024 processing elements (PEs). It can be dynamically reconfigured to work as one or more SIMD (single instruction stream - multiple data stream) and/or MIMD (multiple instruction stream - multiple data stream) machines. A prototype with 30 MC68010 microprocessors, including 16 PEs in the computational engine, is being designed and constructed. The design of the prototype hardware is described, as well as the design tradeoffs that were made. Extending the the current prototype by the addition of a Network Interface Unit (NIU) to each PE is proposed. Such an NIU significantly enhances interprocessor communication by offloading communication overhead from the PE's main CPU. One way to extend the prototype design to a system with 1,024 processors in the computational engine is presented. The powerful reconfiguration capabilities of PASM can be fully utilized only if all tradeoffs influencing reconfiguration are known. Keywords: PASM(Partitionable SIMD/MIMD machine, MIMD(Multiple Instruction Stream - Multiple Data Stream).

The objective of this research is to provide an interconnect design synthesis methodology which facilitates a modular design approach without compromising the global performance. The main tasks of this effort will be the development of the theory for optimal interconnect synthesis from a high-level specification, with emphasis on testability and fault-tolerance asynchronous interface among concurrent computing hardware objects, and the application of this design methodology to physical implementations of parallel processing systems.

The purpose of this study was to evaluate the parallel processing impact of MIMD (Multiple-Instruction Multiple-Data Path) computers on Flight Simulation Software. Basic mathematical functions and arithmetic expressions from typical Flight Simulation Software were selected and run on a MIMD computer to evaluate the improvement in execution time that results from the parallel architecture of this type of computer. Recommendations as to the types of tasks which are optimally suitable for this computer architecture are made, together with the improvement in execution speed to be expected. (Author)

The purpose of this study was to evaluate the parallel processing impact of MIMD (Multiple-Instruction Multiple-Data Path) computers on Flight Simulation Software. Basic mathematical functions and arithmetic expressions from typical Flight Simulation Software were selected and run on a MIMD computer to evaluate the improvement in execution time that results from the parallel architecture of this type of computer. Recommendations as to the types of tasks which are optimally suitable for this computer architecture are made, together with the improvement in execution speed to be expected. (Author)

The research in this paper focuses on the I/O problem associated with a parallel application writing to a single physical disk. Included in our research are the original ideas that led to the first version of the parallel software, subsequent versions of the software derived from lessons learned from benchmark results, and speedup results of each version. The underlying purpose of this software is to process hydrographic data having a complicated, multi-tiered format. The data processing involves reading tens to hundreds of files containing raw data, filtering out extraneous data values, and writing the filtered data to a single file used in additional processing. The problem is not computationally intensive, but bound by the system's file writing capability. Results show that the more responsible the software was for organizing the data before writing, the better the speedup. The critical factor for writing data efficiently involved the limitation of writing data over a single I/O controller. Our parallel software has fantastic utility where system specifications do not allow for the use of parallel file systems, or writing data over multiple I/O controllers.

Network based parallel computing using personal computers is currently a popular choice for concurrent scientific computing. This work evaluates the capabilities and the performance of the AFIT Bimodal Cluster (ABC); a heterogeneous cluster of PCs connected by switched fast Ethernet and using MPICH 1.1 for interprocess communication for parallel digital signal processing using Space Time Adaptive Processing (STAP) as the case study. The MITRE RT_STAP Benchmark version 1.1 is ported and executed on the ABC, as well as on a cluster of six Sun SPARC workstations connected by a Myrinet network (the AFIT NOW), and on a IBM SP for comparison. Modifications to the RT_STAP benchmark source code are done to accommodate the BLAS routines obtained from the ASCI Red project and the FFTPACK from the Netlib repository. Comparative performance analysis of the original and modified versions of the benchmarks executed on the ABC running the LINUX OS is performed, and shows improvements in the sustained Gflop/sec rates. Inter-platform comparative analysis demonstrates ABC's superior computation rates, but also reveals limited machine scalability as a result of severe communication overheads imposed by RT_STAP cornerturn operations. Analysis of experimental data indicates that ABC outperforms AFIT NOW but needs interconnection network improvements to be globally competitive to MPPs such as the IBM SP.

The PEPE Simulation Project has had the responsibility of validating the design of the MSI PEPE by functional simulation. This validation was achieved by demonstrating that the performance characteristics of the MSI PEPE are superior to those of the IC design used in the PHSD demonstrations. Toward achieving design validation, two functional simulation models were constructed; a Calibration Model and a System Verification Model. The purpose of this document is to describe the functions performed by the action sequence chains that comprise these two models.

A procedure is outlined which utilizes parallel processing to solve the inviscid form of the average-passage equation system for multistage turbomachinery along with a description of its implementation in a FORTRAN computer code, MSTAGE. A scheme to reduce the central memory requirements of the program is also detailed. Both the multitasking and I/O routines referred to are specific to the Cray X-MP line of computers and its associated SSD (Solid-State Disk). Results are presented for a simulation of a two-stage rocket engine fuel pump turbine.

The Final Proceedings for VECPAR, 4th International Meeting on Vector and Parallel Processing, 21-23 June 2000, an interdisciplinary conference covering topics in all areas of vector, parallel and distributed computing applied to a broad range of research disciplines with a focus on engineering. The principal topics include: Cellular Automata, Computational Fluid Dynamics, Crash and Structural Analysis, Data Warehousing and Data Mining, Distributed Computing and Operating Systems, Fault Tolerant Systems, Imaging and Graphics, Interconnection Networks, Languages and Tools, Numerical Methods, Parallel and Distributed Algorithms, Real-time and Embedded Systems, Reconfigurable Systems, Linear Algebra Algorithms and Software for Large Scientific Problems, Computer Organization, Image Analysis and Synthesis, and Nonlinear Problems.