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Reproducibility review completed, adding a registration for proper archival and snapshot.

Reproducibility review completed, adding a registration for proper archival and snapshot.

The development of parallel-processing image-analysis codes is generally a challenging task that requires complicated choreography of interprocessor communications. If, however, the image-analysis algorithm is embarrassingly parallel, then the development of a parallel-processing implementation of that algorithm can be a much easier task to accomplish because, by definition, there is little need for communication between the compute processes. I describe the design, implementation, and performance of a parallel-processing image-analysis application, called CRBLASTER, which does cosmic-ray rejection of CCD (charge-coupled device) images using the embarrassingly-parallel L.A.COSMIC algorithm. CRBLASTER is written in C using the high-performance computing industry standard Message Passing Interface (MPI) library. The code has been designed to be used by research scientists who are familiar with C as a parallel-processing computational framework that enables the easy development of parallel-processing image-analysis programs based on embarrassingly-parallel algorithms. The CRBLASTER source code is freely available at the official application website at the National Optical Astronomy Observatory. Removing cosmic rays from a single 800x800 pixel Hubble Space Telescope WFPC2 image takes 44 seconds with the IRAF script lacos_im.cl running on a single core of an Apple Mac Pro computer with two 2.8-GHz quad-core Intel Xeon processors. CRBLASTER is 7.4 times faster processing the same image on a single core on the same machine. Processing the same image with CRBLASTER simultaneously on all 8 cores of the same machine takes 0.875 seconds -- which is a speedup factor of 50.3 times faster than the IRAF script. A detailed analysis is presented of the performance of CRBLASTER using between 1 and 57 processors on a low-power Tilera 700-MHz 64-core TILE64 processor.

The development of parallel-processing image-analysis codes is generally a challenging task that requires complicated choreography of interprocessor communications. If, however, the image-analysis algorithm is embarrassingly parallel, then the development of a parallel-processing implementation of that algorithm can be a much easier task to accomplish because, by definition, there is little need for communication between the compute processes. I describe the design, implementation, and performance of a parallel-processing image-analysis application, called CRBLASTER, which does cosmic-ray rejection of CCD (charge-coupled device) images using the embarrassingly-parallel L.A.COSMIC algorithm. CRBLASTER is written in C using the high-performance computing industry standard Message Passing Interface (MPI) library. The code has been designed to be used by research scientists who are familiar with C as a parallel-processing computational framework that enables the easy development of parallel-processing image-analysis programs based on embarrassingly-parallel algorithms. The CRBLASTER source code is freely available at the official application website at the National Optical Astronomy Observatory. Removing cosmic rays from a single 800x800 pixel Hubble Space Telescope WFPC2 image takes 44 seconds with the IRAF script lacos_im.cl running on a single core of an Apple Mac Pro computer with two 2.8-GHz quad-core Intel Xeon processors. CRBLASTER is 7.4 times faster processing the same image on a single core on the same machine. Processing the same image with CRBLASTER simultaneously on all 8 cores of the same machine takes 0.875 seconds -- which is a speedup factor of 50.3 times faster than the IRAF script. A detailed analysis is presented of the performance of CRBLASTER using between 1 and 57 processors on a low-power Tilera 700-MHz 64-core TILE64 processor.

tilak_agerwala.mpg

We present a computational algorithm for computing short range forces between particles. The algorithm has two distinguishing features. First, it is optimized for multi-processor computers, and will use as many processors as are available. Second, it is optimized for inhomogeneous, dynamic particle distributions; for any distribution the computational load is distributed evenly to all processors, and the communication time is less than 15\% of the total run time. In this talk we present our new algorithm. We developed the program for a grand-challenge problem in cosmology, simulation of the formation of large-scale structure in the universe. This simulation, run on the Thinking Machines Corporation CM-5, uses the particle-particle/particle-mesh (PPPM) \cite{hock_east} algorithm. The particle-particle phase is computed using the algorithm we describe in this paper. We discuss this and other applications.

Many parallel data frameworks have been proposed in recent years that let sequential programs access parallel processing. To capitalize on the benefits of such frameworks, existing code must often be rewritten to the domain-specific languages that each framework supports. This rewriting-tedious and error-prone-also requires developers to choose the framework that best optimizes performance given a specific workload. This paper describes Casper, a novel compiler that automatically retargets sequential Java code for execution on Hadoop, a parallel data processing framework that implements the MapReduce paradigm. Given a sequential code fragment, Casper uses verified lifting to infer a high-level summary expressed in our program specification language that is then compiled for execution on Hadoop. We demonstrate that Casper automatically translates Java benchmarks into Hadoop. The translated results execute on average 3.3x faster than the sequential implementations and scale better, as well, to larger datasets.

A discussion on parallel processing approaches for Linux. Home Page .

A discussion on parallel processing approaches for Linux. Home Page .

This report presents the results of research on the allocation of binary cartesian product database files across several stores (such as disks) which are accessible in parallel so that the average time required to perform the retrieval (by using several parallel accesses) of all buckets specified by a partial-match query is objective of constructing efficient packings of Hamming spheres in hypercubes. The viewpoint of binary cartesian product file allocation thus produced allowed in our research the creation of allocations for two particular sizes of the set of stores such that the average processing time for partial-match queries was smaller than that of the best allocation technique found in the literature for these same two cases. It also provides a framework in which good allocations for other particular sizes of the set of stores, and possibly for general sets of stores, might be found.

The simulation of the propagation of electrical activity in a realistic-geometry computer model of the ventricles of the human heart using the governing reaction-diffusion equation is described. Each model point is represented by the phase 1 Luo-Rudy membrane model, appropriately modified to represent human action potentials. A separate longer-duration action potential waveform was used for the M cells found in the ventricular mid-wall. Cardiac fiber rotation across the ventricular wall was implement via an analytic equation, resulting in a spatially-varying anisotropic conductivity tensor and consequently anisotropic propagation. Since the model comprises approximately 12 million points, parallel processing was used to cut down on simulation time. The model generated acceptably normal electrocardiograms, vector cardiograms and body surface potential maps on the surface of a numerical human torso model. Interestingly, it was found that the intrinsic difference in action potential duration between M cells and other myocardial cells was greatly diminished due to electrotonic coupling.

VMS RTL Parallel Processing Manual

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

The objective of this research is to provide a design methodology for connecting heterogeneous hardware modules that have inherently different functional and timing behavior. With the constraints dictated by the system- level interaction, we need to adopt a modular design approach without compromising the global performance. The main task of this effort will be the development of the theory for optimal interface circuits synthesis from high- level specification, with emphasis on testability and performance. In July-Dec 1991 we have concentrated on the gate-level synthesis of asynchronous control circuits and introducing timing information into the synthesis process to increase circuit performance.

This Memorandum describes work done in mapping image processing algorithms on to transputer arrays. Object classification based on the autocorrelation function has been applied to infrared images. Using the OCCAM programming language, parallel processing techniques have been developed to make use of the concurrency available for communication and calculation. The results for this specific problem are assessed and conclusions drawn on the use of transputers and OCCAM for parallel processing.

The Final Proceedings for VECPAR, 4th International Meeting on Vector and Parallel Processing, 21-23 June 2000, an interdisciplinary conference covering topics in all areas of vector, parallel and distributed computing applied to a broad range of research disciplines with a focus on engineering. The principal topics include: Cellular Automata, Computational Fluid Dynamics, Crash and Structural Analysis, Data Warehousing and Data Mining, Distributed Computing and Operating Systems, Fault Tolerant Systems, Imaging and Graphics, Interconnection Networks, Languages and Tools, Numerical Methods, Parallel and Distributed Algorithms, Real-time and Embedded Systems, Reconfigurable Systems, Linear Algebra Algorithms and Software for Large Scientific Problems, Computer Organization, Image Analysis and Synthesis, and Nonlinear Problems.

DEC OpenVMS RTL Parallel Processing PLs Manual AA PV6JA TK

DEC OpenVMS RTL Parallel Processing PLs Manual AA PV6JA TK

A parallel adaptive dynamic relaxation (ADR) algorithm has been developed for nonlinear structural analysis. This algorithm has minimal memory requirements, is easily parallelizable and scalable to many processors, and is generally very reliable and efficient for highly nonlinear problems. Performance evaluations on single-processor computers have shown that the ADR algorithm is reliable and highly vectorizable, and that it is competitive with direct solution methods for the highly nonlinear problems considered. The present algorithm is implemented on the 512-processor Intel Touchstone DELTA system at Caltech, and it is designed to minimize the extent and frequency of interprocessor communication. The algorithm has been used to solve for the nonlinear static response of two and three dimensional hyperelastic systems involving contact. Impressive relative speedups have been achieved and demonstrate the high scalability of the ADR algorithm. For the class of problems addressed, the ADR algorithm represents a very promising approach for parallel-vector processing.

A capability consisting of software development and experimental techniques has been developed and is described. The capability is integrated into GENOA-PFA to model polymer matrix composite (PMC) structures. The capability considers the physics and mechanics of composite materials and structure by integration of a hierarchical multilevel macro-scale (lamina, laminate, and structure) and micro scale (fiber, matrix, and interface) simulation analyses. The modeling involves (1) ply layering methodology utilizing FEM elements with through-the-thickness representation, (2) simulation of effects of material defects and conditions (e.g., voids, fiber waviness, and residual stress) on global static and cyclic fatigue strengths, (3) including material nonlinearities (by updating properties periodically) and geometrical nonlinearities (by Lagrangian updating), (4) simulating crack initiation. and growth to failure under static, cyclic, creep, and impact loads. (5) progressive fracture analysis to determine durability and damage tolerance. (6) identifying the percent contribution of various possible composite failure modes involved in critical damage events. and (7) determining sensitivities of failure modes to design parameters (e.g., fiber volume fraction, ply thickness, fiber orientation. and adhesive-bond thickness). GENOA-PFA progressive failure analysis is now ready for use to investigate the effects on structural responses to PMC material degradation from damage induced by static, cyclic (fatigue). creep, and impact loading in 2D/3D PMC structures subjected to hygrothermal environments. Its use will significantly facilitate targeting design parameter changes that will be most effective in reducing the probability of a given failure mode occurring.

Recently, networked and cluster computation have become very popular for both signal processing and system simulation. A new language is ideally suited for parallel signal processing applications and system simulation since it allows the programmer to explicitly express the computations that can be performed concurrently. In addition, the new C based parallel language (ace C) for architecture-adaptive programming allows programmers to implement algorithms and system simulation applications on parallel architectures by providing them with the assurance that future parallel architectures will be able to run their applications with a minimum of modification. In this paper, we will focus on some fundamental features of ace C and present a signal processing application (FFT).

A computer program implements parallel- processing algorithms for cor relating images of terrain acquired by stereoscopic pairs of digital stereo cameras on an exploratory robotic vehicle (e.g., a Mars rove r). Such correlations are used to create three-dimensional computatio nal models of the terrain for navigation. In this program, the scene viewed by the cameras is segmented into subimages. Each subimage is assigned to one of a number of central processing units (CPUs) opera ting simultaneously.

This paper will describe the Entry, Descent and Landing simulation tradeoffs and techniques that were used to provide the Monte Carlo data required to approve entry during a critical period just before entry of the Genesis Sample Return Capsule. The same techniques will be used again when Stardust returns on January 15, 2006. Only one hour was available for the simulation which propagated 2000 dispersed entry states to the ground. Creative simulation tradeoffs combined with parallel processing were needed to provide the landing footprint statistics that were an essential part of the Go/NoGo decision that authorized release of the Sample Return Capsule a few hours before entry.

This paper addresses the reservoir design problem in the context of delay-based reservoir computers for multidimensional input signals, parallel architectures, and real-time multitasking. First, an approximating reservoir model is presented in those frameworks that provides an explicit functional link between the reservoir parameters and architecture and its performance in the execution of a specific task. Second, the inference properties of the ridge regression estimator in the multivariate context is used to assess the impact of finite sample training on the decrease of the reservoir capacity. Finally, an empirical study is conducted that shows the adequacy of the theoretical results with the empirical performances exhibited by various reservoir architectures in the execution of several nonlinear tasks with multidimensional inputs. Our results confirm the robustness properties of the parallel reservoir architecture with respect to task misspecification and parameter choice that had already been documented in the literature.

A surface patch/wire junction EFIE method of moment algorithm, JUNCTION, developed by the University of Houston has been implemented in a transputer based parallel processing environment installed in a personal computer. This paper addresses transputer hardware and software options, the JUNCTION algorithm, techniques for parallelizing matrix analysis algorithms, and performance results. The transputer array was found to provide a flexible, low- cost, high performance desktop computing environment for method of moment analysis.... Parallel processing, Computational electromagnets, Visualization.

The intent of this thesis is to answer the question as to whether real time battlefield visualization, once requiring high speed UNIX workstations and specialized parallel processors, can now be now performed on relatively inexpensive off the shelf components. Alternative network topologies were implemented using 10 and 100 megabit-per-second Ethernet cards under the Linux operating system on Pentium based personal computer platforms. Network throughput, processor and video performance benchmark routines were developed to assess the hardware's potential for parallel application in a distributed environment. Code was first ported to the Linux environment. Benchmark routines were then developed and tested on various machines. Dual 200 MHz Pentium Pro processor performance exceeded the dual processor 50 MHz SUN and 40 MHz SGI UNIX workstations currently used for terrain generation by a factor of 30 using a simple ray trace algorithms as a basis for comparison. The Intel Pentium Pro personal computer proved to be a capable platform for generating six to ten frame-per-second terrain simulations. However, Fast Ethernet throughput averages only 2.5 megabytes-per-second, thereby limiting the usefulness of a distributed approach designed to increase performance by dividing workload across the network.

A wavelet function generated by a specially constructed symmetric scale function has been explored for use in edge detection. Experiments showed that relatively refined edge information was obtained in the coarse resolution levels. An edge detection algorithm based on regularization with space-varying parameters has been developed, where the values of the parameters are adaptively determined iteratively. A multiscale edge detection algorithm using a first order regularization filter has been developed. It is demonstrated experimentally that the high localization performance of the filter is combined with high detection performance by using a multiscale integration scheme. Time performances have been evaluated for different embeddings of the wavelet coefficients into two dimensional meshes over typical wavelet based algorithms. Parallel image processing algorithms are under study to identify fundamental parallel limits and to enable fully their parallel application in multiresolution application. Novel graph compounds which can be utilized to enhance communication bandwidth in mesh architectures have been evaluated and appear to offer some promise in image processing.

BCSP, a parallel programming language, is described. It is based on Hoare's Communicating Sequential processes, but uses tail recursion for loops and linked ports for communication. An abstract parallel machine is described that can be used to implement BCSP; the machine description assumes an arbitrary number of processors. (Author)

The Final Proceedings for VECPAR 98 3rd International Meeting on Vector and Parallel Processing, 21 June 1998-23 June 1998. This 15 an Interdisciplinary conference. Topics Include parallel and distributed computing, image processing and synthesis. real-time and embedded systems.

The Final Proceedings for VECPAR 98 3rd International Meeting on Vector and Parallel Processing, 21 June 1998-23 June 1998. This 15 an Interdisciplinary conference. Topics Include parallel and distributed computing, image processing and synthesis. real-time and embedded systems.

Model of the compressing operation of arithmetic multi-row binary codes (MRC) is offered. In this model irregularity allocation of data bit per digits is considered. Procedures and methods of compressing MRC based on this model allow diminish delay of processing are designed (developed).

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

14 p. 28 cm

The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

A new optical parallel arithmetic processing scheme using a nonholographic optoelectronic content-addressable memory (CAM) was proposed. The design of a four-bit CAM-based optical carry look-ahead adder was studied. Compared with existing optoelectronic binary addition approaches, this nonholographic CAM Scheme offers a number of practical advantages, such as faster processing speed and ease of optical implementation and alignment. For an addition of numbers longer than four bits, by incorporating the previous stage's carry, a number of four-bit CLA's can be cascaded. Experimental results were also demonstrated. One paper to the Optics Letters was published.

The PEPE Program was charged with designing an MSI Model PEPE and a full complement of real-time and support software, and represented the second increment of a three-stage PEPE development effort being sponsored by ABMDA. The first stage was a three-year (1969-1971) PEPE IC model feasibility demonstration program conducted by Bell Telephone Laboratories, with SDC and Honeywell assistance during the last year. The third stage, which has just been initiated, is aimed at fabricating a 36-element MSI Model PEPE and producing the required set of software. This last stage is being performed by SDC, employing the Burroughs Corporation as a subcontractor for PEPE fabrication.

The PEPE Program was charged with designing an MSI Model PEPE and a full complement of real-time and support software, and represented the second increment of a three-stage PEPE development effort being sponsored by ABMDA. The first stage was a three-year (1969-1971) PEPE IC model feasibility demonstration program conducted by Bell Telephone Laboratories, with SDC and Honeywell assistance during the last year. The third stage, which has just been initiated, is aimed at fabricating a 36-element MSI Model PEPE and producing the required set of software. This last stage is being performed by SDC, employing the Burroughs Corporation as a subcontractor for PEPE fabrication.

The PEPE Program was charged with designing an MSI Model PEPE and a full complement of real-time and support software, and represented the second increment of a three-stage PEPE development effort being sponsored by ABMDA. The first stage was a three-year (1969-1971) PEPE IC model feasibility demonstration program conducted by Bell Telephone Laboratories, with SDC and Honeywell assistance during the last year. The third stage, which has just been initiated, is aimed at fabricating a 36-element MSI Model PEPE and producing the required set of software. This last stage is being performed by SDC, employing the Burroughs Corporation as a subcontractor for PEPE fabrication.

Research is being carried out on hardware for a new approach to focal plane processing. The hardware involves silicon injection mode devices. These devices provide a natural basis for parallel asynchronous focal plane image preprocessing. The simplicity and novel properties of the devices would permit an independent analog processing channel to be dedicated to every pixel. A laminar architecture built from arrays of the devices would form a two-dimensional (2-D) array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuron-like asynchronous pulse-coded form through the laminar processor. No multiplexing, digitization, or serial processing would occur in the preprocessing state. High performance is expected, based on pulse coding of input currents down to one picoampere with noise referred to input of about 10 femtoamperes. Linear pulse coding has been observed for input currents ranging up to seven orders of magnitude. Low power requirements suggest utility in space and in conjunction with very large arrays. Very low dark current and multispectral capability are possible because of hardware compatibility with the cryogenic environment of high performance detector arrays. The aforementioned hardware development effort is aimed at systems which would integrate image acquisition and image processing.

A survey book made of the high-performance/parallel computing initiatives in the Soviet Union made in 1992, shortly after it's dissolution.

Multidisciplinary design optimization (MDO) for large-scale engineering problems poses many challenges (e.g., the design of an efficient concurrent paradigm for global optimization based on disciplinary analyses, expensive computations over vast data sets, etc.) This work focuses on the application of distributed schemes for massively parallel architectures to MDO problems, as a tool for reducing computation time and solving larger problems. The specific problem considered here is configuration optimization of a high speed civil transport (HSCT), and the efficient parallelization of the embedded paradigm for reasonable design space identification. Two distributed dynamic load balancing techniques (random polling and global round robin with message combining) and two necessary termination detection schemes (global task count and token passing) were implemented and evaluated in terms of effectiveness and scalability to large problem sizes and a thousand processors. The effect of certain parameters on execution time was also inspected. Empirical results demonstrated stable performance and effectiveness for all schemes, and the parametric study showed that the selected algorithmic parameters have a negligible effect on performance.

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