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The matrix element method utilizes ab initio calculations of probability densities as powerful discriminants for processes of interest in experimental particle physics. The method has already been used successfully at previous and current collider experiments. However, the computational complexity of this method for final states with many particles and degrees of freedom sets it at a disadvantage compared to supervised classification methods such as decision trees, k nearest-neighbour, or neural networks. This note presents a concrete implementation of the matrix element technique using graphics processing units. Due to the intrinsic parallelizability of multidimensional integration, dramatic speedups can be readily achieved, which makes the matrix element technique viable for general usage at collider experiments.

This report compiles the results of army research in the area of modeling asynchronous parallel architectures and computation for applications in the areas of digital image and signal processing. The work can be broadly divided into three areas: (1) Case studies of parallel image processing algorithms and tasks, the objective of which is to study the interaction of parallel processes and parallel architectures; (2) Modeling of interconnection networks and (3) Aspects of the problem of modeling parallel processes and parallel architectures.

Two methods are used to speed up the execution of a computational task. One is new technology development and the other is the exploitation of parallelism in the computation. To take an advantage of the parallelism in a task requires the utilization of parallel computer architectures. At a certain high level of abstraction a parallel computer system is represented as a graph where the nodes represent processors, memories, or other devices, and the edges represent the communication links. In this thesis the following problems of parallel processing are studied. First is a theoretical study of topological properties of interconnection networks. Second is a case study of a network design for a real-time system. Lastly, the use of SIMD(Single Instruction Stream Multiple Data Stream) networks for performing 'shuffles'. A general model that can be used to describe networks and systems with arbitrary topologies is developed. Based upon the of morphism of groups, the concept of morphism of systems is developed. The morphism of systems is called quasimorphism and allows a method of comparison between topologically arbitrary parallel computer systems. The quasimorphism is used to study the emulation of one system by another.

The main accomplishments during this grant are in the area of routing algorithms for binary cube networks.

This effort produced an approach for developing software for parallel processing systems based on the parallel object-oriented functional computational model (PROOF). A benefit of this approach is that it allows the software development to be separated from architecture-dependent issues to a great degree. For example, the programmers do not need to be concerned with issues such as synchronization, parallelization, or the topology of the parallel processing system when they address objects in the system. The object-oriented paradigm reflects the parallel structure of the problem space and can represent inherently concurrent behavior. This approach is suitable for MIMD machines and should result in software that is more understandable, modifiable and portable over a variety of parallel computer architectures.

When a store is dropped from a military aircraft at high subsonic, transonic, or supersonic speeds, the aerodynamic forces and moments acting on the store can be sufficient to send the store back into contact with the aircraft. This can cause damage to the aircraft and endanger the life of the crew. Therefore, store separation analysis is used to certify the safety of any proposed drop. This analysis is often based on wind tunnel aerodynamic data or analogy with flight test data from similar configurations. Time accurate computational fluid dynamics (CFD) offers the option of calculating store separation trajectories from first principles. In the Chimera grid scheme a set of independent, overlapping, structured grids are used to decompose the domain of interest. This allows the use of efficient structured grid flow solvers and associated boundary conditions, and allows for grid motion without stretching or regridding. However, these advantages are gained in exchange for the requirement to establish communication links between the overlapping grids via a process referred to as grid assembly.

The objective of this study was to modify an existing parallel particle code based on the direct simulation Monte Carlo (DSMC) method to include a Navier-Stokes (NS) calculation so that a hybrid solution could be developed. In carrying out this work, it was determined that the following five issues had to be addressed before extensive program development of a three dimensional capability was pursued: (1) find a set of one-sided kinetic fluxes that are fully compatible with the DSMC method, (2) develop a finite volume scheme to make use of these one-sided kinetic fluxes, (3) make use of the one-sided kinetic fluxes together with DSMC type boundary conditions at a material surface so that velocity slip and temperature slip arise naturally for near-continuum conditions, (4) find a suitable sampling scheme so that the values of the one-sided fluxes predicted by the NS solution at an interface between the two domains can be converted into the correct distribution of particles to be introduced into the DSMC domain, (5) carry out a suitable number of tests to confirm that the developed concepts are valid, individually and in concert for a hybrid scheme.

The contents include: 1) A brief history of NPB; 2) What is (not) being measured by NPB; 3) Irregular dynamic applications (UA Benchmark); and 4) Wide area distributed computing (NAS Grid Benchmarks-NGB). This paper is presented in viewgraph form.

Perma.cc archive of https://en.wikipedia.org/wiki/Parallel_computing created on 2022-08-13 07:53:19.464194+00:00.

Perma.cc archive of https://en.wikipedia.org/wiki/Parallel_computing created on 2022-08-13 07:53:19.464194+00:00.

Perma.cc archive of https://en.wikipedia.org/wiki/Parallel_computing created on 2022-08-13 07:53:19.464194+00:00.

Perma.cc archive of https://en.wikipedia.org/wiki/Parallel_computing created on 2022-08-13 07:53:19.464194+00:00.

The idea of upgrading performance and utility of computer systems by incorporating parallel processing has been around since at least the 1940s. A significant investment in parallel processing in the 1980s and 1990s has led to an abundance of parallel architectures that due to technical constraints at the time had to rely on multi-chip multi-processing. Unfortunately, their impact on mainstream computing was quite limited. 'Tribal lore' suggests the following reason: while programming for parallelism tends to be easy, turning this parallelism into the 'coarse-grained' type, needed to optimize performance for multi-chip multi-processing (with their high coordination overhead), has been quite hard. The mainstream computing paradigm has always relied on serial code. However, commercially successful processors are entering a second decade of near stagnation in the maximum number of instructions they can issue towards a single computational task in one clock. Alas, the multi-decade reliance on advancing the clock is also coming to an end. The PRAM-On-Chip research project at UMD is reviewed. The project is guided by a fact, an old insight, a recent one and a premise. The fact: Billion transistor chips are here, up from less than 30,000 circa 1980. The older insight: Using a very simple parallel computation model, the parallel random access model (PRAM), the parallel algorithms research community succeeded in developing a general-purpose theory of parallel algorithms that was much richer than any competing approach and is second in magnitude only to serial algorithmics. However, since it did not offer an effective abstraction for multi-chip multi-processors this elegant algorithmic theory remained in the ivory towers of theorists. The PRAM-On-Chip insight: The Billion transistor chip era allows for the first time low-overhead on-chip multi-processors so that the PRAM abstraction becomes effective. The premise: Were the architecture component of PRAM-On-Chip feasible in the 1990s, its parallel programming component would become the mainstream standard. In 1988-90 standard algorithms textbooks chose to include significant PRAM chapters (some still have them). Arguably nothing could stand in the way of teaching them to every student at every computer science program. Programming for concurrency/parallelism is quickly becoming an integral part of mainstream computing. Yet, industry and academia leaders in system software and general-purpose application software have maintained a passive posture: their attention tends to focus too much on getting the best performance out of architectures that originated from a hardware centric approach, or very specific applications, and too little on trying to impact the evolving generation of multi-core and/or multi-threaded general-purpose architectures. We argue, perhaps provocatively, that: (i) limiting programming for parallelism to fit hardware-centric architectures imports the epidemic of programmability problems that has plagued parallel computing into mainstream computing, (ii) it is only a matter of time until the industry will seek convergence based on parallel programmability: the difference in the bottom line between a successful and a less successful strategy on parallel programmability will be too big to ignore, (iii) a more assertive position by such leaders is necessary, and (iv) the PRAM-On-Chip approach offers a more balanced way that avoids these problems. URL: http://www.umiacs.umd.edu/~vishkin/XMT ©2005 Microsoft Corporation. All rights reserved.

The idea of upgrading performance and utility of computer systems by incorporating parallel processing has been around since at least the 1940s. A significant investment in parallel processing in the 1980s and 1990s has led to an abundance of parallel architectures that due to technical constraints at the time had to rely on multi-chip multi-processing. Unfortunately, their impact on mainstream computing was quite limited. 'Tribal lore' suggests the following reason: while programming for parallelism tends to be easy, turning this parallelism into the 'coarse-grained' type, needed to optimize performance for multi-chip multi-processing (with their high coordination overhead), has been quite hard. The mainstream computing paradigm has always relied on serial code. However, commercially successful processors are entering a second decade of near stagnation in the maximum number of instructions they can issue towards a single computational task in one clock. Alas, the multi-decade reliance on advancing the clock is also coming to an end. The PRAM-On-Chip research project at UMD is reviewed. The project is guided by a fact, an old insight, a recent one and a premise. The fact: Billion transistor chips are here, up from less than 30,000 circa 1980. The older insight: Using a very simple parallel computation model, the parallel random access model (PRAM), the parallel algorithms research community succeeded in developing a general-purpose theory of parallel algorithms that was much richer than any competing approach and is second in magnitude only to serial algorithmics. However, since it did not offer an effective abstraction for multi-chip multi-processors this elegant algorithmic theory remained in the ivory towers of theorists. The PRAM-On-Chip insight: The Billion transistor chip era allows for the first time low-overhead on-chip multi-processors so that the PRAM abstraction becomes effective. The premise: Were the architecture component of PRAM-On-Chip feasible in the 1990s, its parallel programming component would become the mainstream standard. In 1988-90 standard algorithms textbooks chose to include significant PRAM chapters (some still have them). Arguably nothing could stand in the way of teaching them to every student at every computer science program. Programming for concurrency/parallelism is quickly becoming an integral part of mainstream computing. Yet, industry and academia leaders in system software and general-purpose application software have maintained a passive posture: their attention tends to focus too much on getting the best performance out of architectures that originated from a hardware centric approach, or very specific applications, and too little on trying to impact the evolving generation of multi-core and/or multi-threaded general-purpose architectures. We argue, perhaps provocatively, that: (i) limiting programming for parallelism to fit hardware-centric architectures imports the epidemic of programmability problems that has plagued parallel computing into mainstream computing, (ii) it is only a matter of time until the industry will seek convergence based on parallel programmability: the difference in the bottom line between a successful and a less successful strategy on parallel programmability will be too big to ignore, (iii) a more assertive position by such leaders is necessary, and (iv) the PRAM-On-Chip approach offers a more balanced way that avoids these problems. URL: http://www.umiacs.umd.edu/~vishkin/XMT ©2005 Microsoft Corporation. All rights reserved.

polski test turinga gnu marek nowicki

The use of computers in statistical physics is common because the sheer number of equations that describe the behavior of an entire system particle by particle often makes it impossible to solve them exactly. Monte Carlo methods form a particularly important class of numerical methods for solving problems in statistical physics. Although these methods are simple in principle, their proper use requires a good command of statistical mechanics, as well as considerable computational resources. The aim of this paper is to demonstrate how the usage of widely accessible graphics cards on personal computers can elevate the computing power in Monte Carlo simulations by orders of magnitude, thus allowing live classroom demonstration of phenomena that would otherwise be out of reach. As an example, we use the public goods game on a square lattice where two strategies compete for common resources in a social dilemma situation. We show that the second-order phase transition to an absorbing phase in the system belongs to the directed percolation universality class, and we compare the time needed to arrive at this result by means of the main processor and by means of a suitable graphics card. Parallel computing on graphics processing units has been developed actively during the last decade, to the point where today the learning curve for entry is anything but steep for those familiar with programming. The subject is thus ripe for inclusion in graduate and advanced undergraduate curricula, and we hope that this paper will facilitate this process in the realm of physics education. To that end, we provide a documented source code for an easy reproduction of presented results and for further development of Monte Carlo simulations of similar systems.

The use of computers in statistical physics is common because the sheer number of equations that describe the behavior of an entire system particle by particle often makes it impossible to solve them exactly. Monte Carlo methods form a particularly important class of numerical methods for solving problems in statistical physics. Although these methods are simple in principle, their proper use requires a good command of statistical mechanics, as well as considerable computational resources. The aim of this paper is to demonstrate how the usage of widely accessible graphics cards on personal computers can elevate the computing power in Monte Carlo simulations by orders of magnitude, thus allowing live classroom demonstration of phenomena that would otherwise be out of reach. As an example, we use the public goods game on a square lattice where two strategies compete for common resources in a social dilemma situation. We show that the second-order phase transition to an absorbing phase in the system belongs to the directed percolation universality class, and we compare the time needed to arrive at this result by means of the main processor and by means of a suitable graphics card. Parallel computing on graphics processing units has been developed actively during the last decade, to the point where today the learning curve for entry is anything but steep for those familiar with programming. The subject is thus ripe for inclusion in graduate and advanced undergraduate curricula, and we hope that this paper will facilitate this process in the realm of physics education. To that end, we provide a documented source code for an easy reproduction of presented results and for further development of Monte Carlo simulations of similar systems.

Parallel Computing 1990: Volume 15 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-08_14_3 . Next issue: sim_parallel-computing_1990_15_contents .

Parallel Computing 1990: Volume 15 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-08_14_3 . Next issue: sim_parallel-computing_1990_15_contents .

Parallel Computing 1990: Volume 15 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-08_14_3 . Next issue: sim_parallel-computing_1990_15_contents .

Parallel Computing 1990: Volume 15 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-08_14_3 . Next issue: sim_parallel-computing_1990_15_contents .

Parallel Computing 1990: Volume 15 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-08_14_3 . Next issue: sim_parallel-computing_1990_15_contents .

Wide Area Information Servers Project Documentation, Scanned and uploaded in 2013.

The development of Internet wide resources for general purpose parallel computing poses the challenging task of matching computation and communication complexity. A number of parallel computing models exist that address this for traditional parallel architectures, and there are a number of emerging models that attempt to do this for large scale Internet-based systems like computational grids. In this survey we cover the three fundamental aspects -- application, architecture and model, and we show how they have been developed over the last decade. We also cover programming tools that are currently being used for parallel programming in computational grids. The trend in conventional computational models are to put emphasis on efficient communication between participating nodes by adapting different types of communication to network conditions. Effects of dynamism and uncertainties that arise in large scale systems are evidently important to understand and yet there is currently little work that addresses this from a parallel computing perspective.

The development of Internet wide resources for general purpose parallel computing poses the challenging task of matching computation and communication complexity. A number of parallel computing models exist that address this for traditional parallel architectures, and there are a number of emerging models that attempt to do this for large scale Internet-based systems like computational grids. In this survey we cover the three fundamental aspects -- application, architecture and model, and we show how they have been developed over the last decade. We also cover programming tools that are currently being used for parallel programming in computational grids. The trend in conventional computational models are to put emphasis on efficient communication between participating nodes by adapting different types of communication to network conditions. Effects of dynamism and uncertainties that arise in large scale systems are evidently important to understand and yet there is currently little work that addresses this from a parallel computing perspective.

The development of Internet wide resources for general purpose parallel computing poses the challenging task of matching computation and communication complexity. A number of parallel computing models exist that address this for traditional parallel architectures, and there are a number of emerging models that attempt to do this for large scale Internet-based systems like computational grids. In this survey we cover the three fundamental aspects -- application, architecture and model, and we show how they have been developed over the last decade. We also cover programming tools that are currently being used for parallel programming in computational grids. The trend in conventional computational models are to put emphasis on efficient communication between participating nodes by adapting different types of communication to network conditions. Effects of dynamism and uncertainties that arise in large scale systems are evidently important to understand and yet there is currently little work that addresses this from a parallel computing perspective.

Computation of optimal cycle mean in a directed weighted graph has many applications in program analysis, performance verification in particular. In this paper we propose a data-parallel algorithmic solution to the problem and show how the computation of optimal cycle mean can be efficiently accelerated by means of CUDA technology. We show how the problem of computation of optimal cycle mean is decomposed into a sequence of data-parallel graph computation primitives and show how these primitives can be implemented and optimized for CUDA computation. Finally, we report a fivefold experimental speed up on graphs representing models of distributed systems when compared to best sequential algorithms.

Computation of optimal cycle mean in a directed weighted graph has many applications in program analysis, performance verification in particular. In this paper we propose a data-parallel algorithmic solution to the problem and show how the computation of optimal cycle mean can be efficiently accelerated by means of CUDA technology. We show how the problem of computation of optimal cycle mean is decomposed into a sequence of data-parallel graph computation primitives and show how these primitives can be implemented and optimized for CUDA computation. Finally, we report a fivefold experimental speed up on graphs representing models of distributed systems when compared to best sequential algorithms.

The research of this project concerned the investigation of the suitability of the SOR iteration as a preconditioner for the GMRES method for solving large sparse nonsymmetric systems of linear equations. Preliminary results on a serial computer (RS 6000) showed that SOR was indeed a good preconditioner, at least for the convection-diffusion equations used in this study. This was in contradiction to various statements that had appeared in the literature, questioning the suitability of SOR as a preconditioner. These experiments using a serial computer were described more completely in previous semi-annual reports as well as in. The second phase of this project was to develop parallel codes for the Intel Paragon at NASA-Langley and the Center for Advanced Computing Research at Caltech, and the IBM SP-2 at NASA-Langley and NASA-Ames. Highly parallel codes were developed. Indeed, an unexpected result was the superlinear speedup in some cases due to better cache utilization as the problem sizes and number of processors increased. Preliminary results on these parallel experiments were given.

The research of this project concerned the investigation of the suitability of the SOR iteration as a preconditioner for the GMRES method for solving large sparse nonsymmetric systems of linear equations. Preliminary results on a serial computer (RS 6000) showed that SOR was indeed a good preconditioner, at least for the convection-diffusion equations used in this study. This was in contradiction to various statements that had appeared in the literature, questioning the suitability of SOR as a preconditioner. These experiments using a serial computer were described more completely in previous semi-annual reports as well as in. The second phase of this project was to develop parallel codes for the Intel Paragon at NASA-Langley and the Center for Advanced Computing Research at Caltech, and the IBM SP-2 at NASA-Langley and NASA-Ames. Highly parallel codes were developed. Indeed, an unexpected result was the superlinear speedup in some cases due to better cache utilization as the problem sizes and number of processors increased. Preliminary results on these parallel experiments were given.

Establishing a test-bed for clustered parallel computing is reported along with performance evaluation of various clusters for a number of applications/parallel algorithms.

Establishing a test-bed for clustered parallel computing is reported along with performance evaluation of various clusters for a number of applications/parallel algorithms.

Parallel Computing 1991: Volume 17 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-12_16_2-3 . Next issue: sim_parallel-computing_1991-04_17_1 .

Parallel Computing 1991: Volume 17 , Issue Index. Digitized from IA1652917-03 . Previous issue: sim_parallel-computing_1990-12_16_2-3 . Next issue: sim_parallel-computing_1991-04_17_1 .

788 p. ; 27 cm

We introduce process-oriented programming as a natural extension of object-oriented programming for parallel computing. It is based on the observation that every class of an object-oriented language can be instantiated as a process, accessible via a remote pointer. The introduction of process pointers requires no syntax extension, identifies processes with programming objects, and enables processes to exchange information simply by executing remote methods. Process-oriented programming is a high-level language alternative to multithreading, MPI and many other languages, environments and tools currently used for parallel computations. It implements natural object-based parallelism using only minimal syntax extension of existing languages, such as C++ and Python, and has therefore the potential to lead to widespread adoption of parallel programming. We implemented a prototype system for running processes using C++ with MPI and used it to compute a large three-dimensional Fourier transform on a computer cluster built of commodity hardware components. Three-dimensional Fourier transform is a prototype of a data-intensive application with a complex data-access pattern. The process-oriented code is only a few hundred lines long, and attains very high data throughput by achieving massive parallelism and maximizing hardware utilization.

We introduce process-oriented programming as a natural extension of object-oriented programming for parallel computing. It is based on the observation that every class of an object-oriented language can be instantiated as a process, accessible via a remote pointer. The introduction of process pointers requires no syntax extension, identifies processes with programming objects, and enables processes to exchange information simply by executing remote methods. Process-oriented programming is a high-level language alternative to multithreading, MPI and many other languages, environments and tools currently used for parallel computations. It implements natural object-based parallelism using only minimal syntax extension of existing languages, such as C++ and Python, and has therefore the potential to lead to widespread adoption of parallel programming. We implemented a prototype system for running processes using C++ with MPI and used it to compute a large three-dimensional Fourier transform on a computer cluster built of commodity hardware components. Three-dimensional Fourier transform is a prototype of a data-intensive application with a complex data-access pattern. The process-oriented code is only a few hundred lines long, and attains very high data throughput by achieving massive parallelism and maximizing hardware utilization.

Literaturangaben

First Class

Parallel Computing 1984: Volume 1 , Issue Index. Digitized from IA1652917-03 . Next issue: sim_parallel-computing_1984-08_1_1 .

Markov chain Monte Carlo (MCMC) is the predominant tool used in Bayesian parameter estimation for hierarchical models. When the model expands due to an increasing number of hierarchical levels, number of groups at a particular level, or number of observations in each group, a fully Bayesian analysis via MCMC can easily become computationally demanding, even intractable. We illustrate how the steps in an MCMC for hierarchical models are predominantly one of two types: conditionally independent draws or low-dimensional draws based on summary statistics of parameters at higher levels of the hierarchy. Parallel computing can increase efficiency by performing embarrassingly parallel computations for conditionally independent draws and calculating the summary statistics using parallel reductions. During the MCMC algorithm, we record running means and means of squared parameter values to allow convergence diagnosis and posterior inference while avoiding the costly memory transfer bottleneck. We demonstrate the effectiveness of the algorithm on a model motivated by next generation sequencing data, and we release our implementation in R packages fbseq and fbseqCUDA.

Whether or not the problem of finding maximal independent sets (MIS) in hypergraphs is in (R)NC is one of the fundamental problems in the theory of parallel computing. Unlike the well-understood case of MIS in graphs, for the hypergraph problem, our knowledge is quite limited despite considerable work. It is known that the problem is in \emph{RNC} when the edges of the hypergraph have constant size. For general hypergraphs with $n$ vertices and $m$ edges, the fastest previously known algorithm works in time $O(\sqrt{n})$ with $\text{poly}(m,n)$ processors. In this paper we give an EREW PRAM algorithm that works in time $n^{o(1)}$ with $\text{poly}(m,n)$ processors on general hypergraphs satisfying $m \leq n^{\frac{\log^{(2)}n}{8(\log^{(3)}n)^2}}$, where $\log^{(2)}n = \log\log n$ and $\log^{(3)}n = \log\log\log n$. Our algorithm is based on a sampling idea that reduces the dimension of the hypergraph and employs the algorithm for constant dimension hypergraphs as a subroutine.

Whether or not the problem of finding maximal independent sets (MIS) in hypergraphs is in (R)NC is one of the fundamental problems in the theory of parallel computing. Unlike the well-understood case of MIS in graphs, for the hypergraph problem, our knowledge is quite limited despite considerable work. It is known that the problem is in \emph{RNC} when the edges of the hypergraph have constant size. For general hypergraphs with $n$ vertices and $m$ edges, the fastest previously known algorithm works in time $O(\sqrt{n})$ with $\text{poly}(m,n)$ processors. In this paper we give an EREW PRAM algorithm that works in time $n^{o(1)}$ with $\text{poly}(m,n)$ processors on general hypergraphs satisfying $m \leq n^{\frac{\log^{(2)}n}{8(\log^{(3)}n)^2}}$, where $\log^{(2)}n = \log\log n$ and $\log^{(3)}n = \log\log\log n$. Our algorithm is based on a sampling idea that reduces the dimension of the hypergraph and employs the algorithm for constant dimension hypergraphs as a subroutine.

Whether or not the problem of finding maximal independent sets (MIS) in hypergraphs is in (R)NC is one of the fundamental problems in the theory of parallel computing. Unlike the well-understood case of MIS in graphs, for the hypergraph problem, our knowledge is quite limited despite considerable work. It is known that the problem is in \emph{RNC} when the edges of the hypergraph have constant size. For general hypergraphs with $n$ vertices and $m$ edges, the fastest previously known algorithm works in time $O(\sqrt{n})$ with $\text{poly}(m,n)$ processors. In this paper we give an EREW PRAM algorithm that works in time $n^{o(1)}$ with $\text{poly}(m,n)$ processors on general hypergraphs satisfying $m \leq n^{\frac{\log^{(2)}n}{8(\log^{(3)}n)^2}}$, where $\log^{(2)}n = \log\log n$ and $\log^{(3)}n = \log\log\log n$. Our algorithm is based on a sampling idea that reduces the dimension of the hypergraph and employs the algorithm for constant dimension hypergraphs as a subroutine.

{\sc top-c} (Task Oriented Parallel C) is a freely available package for parallel computing. It is designed to be easy to learn and to have good tolerance for the high latencies that are common in commodity networks of computers. It has been successfully used in a wide range of examples, providing linear speedup with the number of computers. A brief overview of {\sc top-c} is provided, along with recent experience with cosmic ray physics simulations.

We present a computational algorithm for computing short range forces between particles. The algorithm has two distinguishing features. First, it is optimized for multi-processor computers, and will use as many processors as are available. Second, it is optimized for inhomogeneous, dynamic particle distributions; for any distribution the computational load is distributed evenly to all processors, and the communication time is less than 15\% of the total run time. In this talk we present our new algorithm. We developed the program for a grand-challenge problem in cosmology, simulation of the formation of large-scale structure in the universe. This simulation, run on the Thinking Machines Corporation CM-5, uses the particle-particle/particle-mesh (PPPM) \cite{hock_east} algorithm. The particle-particle phase is computed using the algorithm we describe in this paper. We discuss this and other applications.

We present a computational algorithm for computing short range forces between particles. The algorithm has two distinguishing features. First, it is optimized for multi-processor computers, and will use as many processors as are available. Second, it is optimized for inhomogeneous, dynamic particle distributions; for any distribution the computational load is distributed evenly to all processors, and the communication time is less than 15\% of the total run time. In this talk we present our new algorithm. We developed the program for a grand-challenge problem in cosmology, simulation of the formation of large-scale structure in the universe. This simulation, run on the Thinking Machines Corporation CM-5, uses the particle-particle/particle-mesh (PPPM) \cite{hock_east} algorithm. The particle-particle phase is computed using the algorithm we describe in this paper. We discuss this and other applications.

Trimester 2 2022/2023