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As transistor sizes shrink and we approach the end of Moore's law interconnects-both on-chip and off-chip-will represent the biggest bottleneck for embedded systems designers. Several groups are researching optical interconnects to cope with this tread. Optical interconnects enable new system architectures. These new architectures in turn require new methods for high-level application mapping and hardware/software co-design. In this presentation, we discuss high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessors. We focus on designs that are streamlined for one or more digital signal processing (DSP) applications. That is, we seek to synthesize an application-specific interconnect topology for a multiprocessor DSP design. We show that flexible interconnect topologies that allow single- hop communication between processors offer advantages for reduced power and latency. We have previously shown that multiprocessor scheduling algorithms can deadlock in the general case of a topology graph that is not strongly connected or if communication is limited to be single hop. We have also demonstrated an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock 1. In this presentation we discuss the advantages of performing application scheduling and interconnect synthesis jointly and present a probabilistic scheduling/ interconnect algorithm utilizing graph isomorphism to pare the design space. We demonstrate the performance advantages that an application-specific interconnect topology can produce for several DSP beachmarks.

In this paper we consider the scheduling problem of hard real-time systems composed of periodic constrained-deadline tasks upon identical multiprocessor platforms. We assume that tasks are scheduled by using the global-EDF scheduler. We establish an exact schedulability test for this scheduler by exploiting on the one hand its predictability property and by providing on the other hand a feasibility interval so that if it is possible to find a valid schedule for all the jobs contained in this interval, then the whole system will be stamped feasible. In addition, we show by means of a counterexample that the feasibility interval, and thus the schedulability test, proposed by Leung [Leung 1989] is incorrect and we show which arguments are actually incorrect.

This document presents a language and graph representation designed to aid in the partitioning of large signal processing applications into tasks to run on a multiprocessor. This language compiles directly into a program graph upon which optimizations are performed to find the optimal task configuration. The optimal task configuration is one in which computation-to-communication is minimized while throughput is maximized. The language and graph are designed to express coarse-grain parallelism so that large communication delays and task overhead do not outweigh the speedup achieved by exploiting the parallelism in the application. The data flow model underlying the graph representation is based on a distributed, loosely-coupled multiprocessor concept which supports tagged data flow at the operating system level. The approach utilized in the graph and language is to insert specific, data, routing operators into the data flow graph defined by the application. These operators shape and route data through the application and express all the coarse-grain parallelism which is exploitable in the model. Data routing operators are parameterized to reflect the degree of parallelism, i.e., the number of parallel tasks in a partition of the application. The graph constructs also contain sufficient information to describe fully the task structure of the application. Given the characteristics of the partition, the programmer can define a standard by which the 'goodness' of the partition is evaluated. Given this standard, algorithms to perform the evaluation can be developed. The ultimate goal is the development of algorithms to perform the entire partitioning process automatically.

This paper presents the implementations and results of a model problem, the Symmetric Successive Over-Relaxation (SSOR) simulated application benchmark from the NAS Parallel Benchmark suite for three different parallel processors. SSOR is an iterative implicit method that partitions the left hand side matrix into a lower triangular matrix and an upper triangular matrix. The machines used are an eight processor Cray Y-MP, a 32k processor Thinking Machines Corp. CM-2 and a 128 processor Intel iPSC/860. The primary difficulty in implementing SSOR on a parallel machine lies in finding enough parallelism within the triangular solves to keep a large number of processors active. A data mapping useful for distributed memory architectures is presented. The results show that the eight processor Cray Y-MP has the best performance among the three machines.

This paper presents the implementations and results of a model problem, the Symmetric Successive Over-Relaxation (SSOR) simulated application benchmark from the NAS Parallel Benchmark suite for three different parallel processors. SSOR is an iterative implicit method that partitions the left hand side matrix into a lower triangular matrix and an upper triangular matrix. The machines used are an eight processor Cray Y-MP, a 32k processor Thinking Machines Corp. CM-2 and a 128 processor Intel iPSC/860. The primary difficulty in implementing SSOR on a parallel machine lies in finding enough parallelism within the triangular solves to keep a large number of processors active. A data mapping useful for distributed memory architectures is presented. The results show that the eight processor Cray Y-MP has the best performance among the three machines.

This paper presents the implementations and results of a model problem, the Symmetric Successive Over-Relaxation (SSOR) simulated application benchmark from the NAS Parallel Benchmark suite for three different parallel processors. SSOR is an iterative implicit method that partitions the left hand side matrix into a lower triangular matrix and an upper triangular matrix. The machines used are an eight processor Cray Y-MP, a 32k processor Thinking Machines Corp. CM-2 and a 128 processor Intel iPSC/860. The primary difficulty in implementing SSOR on a parallel machine lies in finding enough parallelism within the triangular solves to keep a large number of processors active. A data mapping useful for distributed memory architectures is presented. The results show that the eight processor Cray Y-MP has the best performance among the three machines.

This paper presents the implementations and results of a model problem, the Symmetric Successive Over-Relaxation (SSOR) simulated application benchmark from the NAS Parallel Benchmark suite for three different parallel processors. SSOR is an iterative implicit method that partitions the left hand side matrix into a lower triangular matrix and an upper triangular matrix. The machines used are an eight processor Cray Y-MP, a 32k processor Thinking Machines Corp. CM-2 and a 128 processor Intel iPSC/860. The primary difficulty in implementing SSOR on a parallel machine lies in finding enough parallelism within the triangular solves to keep a large number of processors active. A data mapping useful for distributed memory architectures is presented. The results show that the eight processor Cray Y-MP has the best performance among the three machines.

The Spring project has been very active in multiple areas of real-time computing. We have developed significant results in many aspects of real-time scheduling, in real-time operating system design, in real-time transactions, and in time constrained communication protocols. We have also made progress in implementing a software (simulation) testbed, in developing a hardware operating system kernel testbed called SpringNet, and in implementing real-time transactions on a hardware testbed called CARAT. We have also begun a substantial research effort concerning dependable real-time systems. In the following sections we provide a brief overview of the status and plans for the Spring project as a whole.

The memory model of a shared-memory multiprocessor is a contract between the designer and programmer of the multiprocessor. The sequential consistency memory model specifies a total order among the memory (read and write) events performed at each processor. A trace of a memory system satisfies sequential consistency if there exists a total order of all memory events in the trace that is both consistent with the total order at each processor and has the property that every read event to a location returns the value of the last write to that location. Descriptions of shared-memory systems are typically parameterized by the number of processors, the number of memory locations, and the number of data values. It has been shown that even for finite parameter values, verifying sequential consistency on general shared-memory systems is undecidable. We observe that, in practice, shared-memory systems satisfy the properties of causality and data independence. Causality is the property that values of read events flow from values of write events. Data independence is the property that all traces can be generated by renaming data values from traces where the written values are distinct from each other. If a causal and data independent system also has the property that the logical order of write events to each location is identical to their temporal order, then sequential consistency can be verified algorithmically. Specifically, we present a model checking algorithm to verify sequential consistency on such systems for a finite number of processors and memory locations and an arbitrary number of data values.

In this paper, we propose a synchronous protocol without periodicity for scheduling multi-mode real-time systems upon identical multiprocessor platforms. Our proposal can be considered to be a multiprocessor extension of the uniprocessor protocol called "Minimal Single Offset protocol".

22 p. 28 cm

From the bitsavers.org collection, a scanned-in computer-related document. univac :: 1100 :: brochures :: S6818r3 Sperry Series 1100 Multiprocessors Brochure Oct83

Exploiting the performance potential of distributed memory machines requires a careful distribution of data across the processors. Vienna FORTRAN is a language extension of FORTRAN which provides the user with a wide range of facilities for such mapping of data structures. However, programs in Vienna FORTRAN are written using global data references. Thus, the user has the advantage of a shared memory programming paradigm while explicitly controlling the placement of data. The basic features of Vienna FORTRAN are presented along with a set of examples illustrating the use of these features.

Multi-core processors support all modern electronic devices nowadays. However, temperature and performance management are one of the most critical issues in the design of today’s microprocessors. In this paper, we propose a framework by using an optimal control method based on fan speed and frequency control of the multi-core processor. The goal is to optimize performance and at the same time avoid violating an expected temperature. Our proposed method uses a high-precision thermal and power model for multi-core processors. This method is validated on asymmetric ODROID-XU4 multi-core processor. The experimental results show the ability of the proposed method to achieve the adequate trade-off between performance and temperature control.

This dissertation examines the solutions, based on software, adaptive backoff algorithms, to two computer network problems and a shared-memory multiprocessor problem. For each problem we define a cost metric against which we adjust the adaptive backoff algorithm. This dissertation's unifying theme is that, when possible, backoff algorithms should tune themselves to their environment. The algorithms that we propose are software remedies to hardware shortcomings; they do not require changes to the hardware, however warranted these changes might be, but they may require that we periodically measure certain expected values or probability distributions. We devote the majority of this dissertation to studying buffer overflow as it occurs during reliable, local area network, multicast. We develop a multiple round, soft real-time algorithm that trades latency for computational overhead: an n-round multicast is slower but suffers less computational overhead than an \201n+1\202-round multicast. Our prototype system measures the buffer service time distribution and employs it to calculate the algorithm's retransmission timeouts. We develop a preemptive, limited buffer queueing model that accurately models an operating system's communication protocol processes. We study a memory contention problem that occurs during synchronization of bus-oriented, shared-memory multiprocessors with snoopy, invalidation-based caches. The connection occurs when such multiprocessors cache lock variables, lack advanced synchronization instructions, and synchronize with a test-and-set instruction embedded in a busy waiting loop. This type of synchronization structure has been dubbed a spin-lock. When a spin-lock is released, the cache invalidation signal can cause a burst of memory activity that we call an invalidation storm. Remedies for invalidation storms can waste memory cycles. Our spin-lock backoff algorithm wastes twenty to fifty percent fewer cycles than a recently proposed algorithm. We

Several variations of cache-based checkpointing for rollback error recovery in shared-memory multiprocessors have been recently developed. By modifying the cache replacement policy, these techniques use the inherent redundancy in the memory hierarchy to periodically checkpoint the computation state. Three schemes, different in the manner in which they avoid rollback propagation, are evaluated in this paper. By simulation with address traces from parallel applications running on an Encore Multimax shared-memory multiprocessor, we evaluate the performance effect of integrating the recovery schemes in the cache coherence protocol. Our results indicate that the cache- based schemes can provide checkpointing capability with low performance overhead but uncontrollable high variability in the checkpoint interval.... Fault- tolerant computing, Cache-based checkpointing and rollback recovery, Shared- memory multiprocessors, Trace-driven simulation.

Software tends to misbehave more often than we would like due to bugs and security attacks. The good news is that there are a variety of dynamic program monitoring tools (which we call 'lifeguards') that can detect and sometimes repair these problems at runtime. The bad news, however, is that these lifeguards (e.g., Valgrind) often slow down execution by an order of magnitude or more, thereby limiting their usefulness. With the emergence of chip multiprocessing as the dominant computing platform, the raw horsepower for performing these monitoring tasks may exist on-chip. In order for the lifeguards to effectively exploit this raw horsepower, however, they need two forms of additional support: the ability to unobtrusively observe the dynamic behavior of the monitored application, and the ability to rewind that application for the sake of repairing a problem. In this joint project that we recently started at Intel Research Pittsburgh and Carnegie Mellon University, we are exploring whether this support can be provided by a single new architectural mechanism: a log that is captured by the hardware, managed by the system, and exposed to the lifeguard software.Our initial results using three diverse lifeguards demonstrate an order-of-magnitude speedup relative to equivalent tools written in Valgrind. Our design also includes a prediction-based compression scheme that reduces the log-related bandwidth and storage requirements by an order of magnitude, to less than one byte per instruction. ©2006 Microsoft Corporation. All rights reserved.

Parallel computation is an area in which software technology lags considerably behind hardware technology. The need for parallel computing in a number of applications (e.g., scientific computing, machine vision, artificial intelligence) is unquestioned, and computers with hundreds of processors are now readily available (for instance, the Butterfly or the many derivatives of the Cosmic Cube). However, these machines are programmed in essentially the same way as existing sequential machines. The best available parallel programming languages are variants of standard sequential languages, with extensions to let the programmer explicitly divide a program into tasks and pass information between those tasks. Although designers of these languages claim that they are no harder to use than conventional sequential ones, programmers still face the problem of figuring out how to partition their application into tasks in addition to the usual problem of translating it into a program. An appealing alternative is to leave partitioning of programs to compilers. By hiding partitioning problems from programmers, this approach should make multi-processor computers easier to program than they are now. Unfortunately efforts to develop parallelizing compilers have so far been rather unsuccessful.

One of the most important issues in parallel processing is the mapping of workload to processors. This paper considers a large class of problems having a high degree of potential fine grained parallelism, and execution requirements that are either not predictable, or are too costly to predict. The main issues in mapping such a problem onto medium scale multiprocessors are those of aggregation and assignment. We study a method of parameterized aggregation that makes few assumptions about the workload. The mapping of aggregate units of work onto processors is uniform, and exploits locality of workload intensity to balance the unknown workload. In general, a finer aggregate granularity leads to a better balance at the price of increased communication/synchronization costs; the aggregation parameters can be adjusted to find a reasonable granularity. The effectiveness of this scheme is demonstrated on three model problems: an adaptive one-dimensional fluid dynamics problem with message passing, a sparse triangular linear system solver on both a shared memory and a message-passing machine, and a two-dimensional time-driven battlefield simulation employing message passing. Using the model problems, the tradeoffs are studied between balanced workload and the communication/synchronization costs. Finally, an analytical model is used to explain why the method balances workload and minimizes the variance in system behavior.

30 p. 28 cm

In article the variant of practical realization of system binaural hearing inherent is offered to the person and many representatives of fauna. Properties binaural hearing are realized by operations above images of the acoustic signals received from a array of microphones. Realization assumes the coherent, synchronized work of 3 microprocessors which are carrying out reading of signals from 4 microphones through two 16 digit ADC with frequency of digitization 100 kHz on each channel with synchronization between channels with accuracy 5 uS. In realized the Flash card in capacity 2 GB and the microprocessor realizing interface USB from the personal COMPUTER is included. Realization provides independent work of system and together with the personal COMPUTER. The system has properties not inherent in hearing of the person – zero time of adaptation at transition from a strong signal to weak and on the contrary, localization of very short signals.

Book Source: Digital Library of India Item 2015.191727 dc.contributor.author: Adarshpal Singh Sethi dc.date.accessioned: 2015-07-08T01:09:06Z dc.date.available: 2015-07-08T01:09:06Z dc.date.digitalpublicationdate: 2005-08-20 dc.identifier.barcode: 1990010090218 dc.identifier.origpath: /rawdataupload/upload/0090/218 dc.identifier.copyno: 1 dc.identifier.uri: http://www.new.dli.ernet.in/handle/2015/191727 dc.description.scannerno: 12 dc.description.scanningcentre: IIIT, Allahabad dc.description.main: 1 dc.description.tagged: 0 dc.description.totalpages: 102 dc.format.mimetype: application/pdf dc.language.iso: English dc.rights: Out_of_copyright dc.source.library: Indian Institute Of Technology Kanpur dc.subject.classification: Technology dc.subject.classification: Engineering. Technology In General dc.subject.classification: Computer Science Engineering dc.title: New Analytic Models For Multiprocessors With Various Interconnection Structures

The computational requirements for an adaptive solution of unsteady problems change as the simulation progresses. This causes workload imbalance among processors on a parallel machine which, in turn, requires significant data movement at runtime. We present a new dynamic load-balancing framework, called JOVE, that balances the workload across all processors with a global view. Whenever the computational mesh is adapted, JOVE is activated to eliminate the load imbalance. JOVE has been implemented on an IBM SP2 distributed-memory machine in MPI for portability. Experimental results for two model meshes demonstrate that mesh adaption with load balancing gives more than a sixfold improvement over one without load balancing. We also show that JOVE gives a 24-fold speedup on 64 processors compared to sequential execution.

There are at least two-critical components required to obtain extremely fast methods for solving sparse linear systems. One is the use of efficient and robust numerical algorithms, and the other is the employment of effective techniques for delivering a large amount of computing power. These requirements can conflict with one another in a variety of ways. Many modern methods of solving reasonably general classes of linear systems involve a degree of implicitness; this implicitness can limit the amount of available concurrency. When Krylov space linear solvers are used, the choice of preconditioner can play a major role in determining the operation count of the resulting algorithm. Unfortunately, some of the most powerful preconditioners are obtained by using incompletely factored matrices. To apply these preconditioners, we must repeatedly solve sparse triangular systems. The efficiency with which such solutions could be carried out was characterized by Saad and Schultz. Sparse triangular systems arising from a range of problems have been solved efficiently on a number of shared memory architectures 1,3,4,9. Because data dependencies limit the concurrency available from a sparse triangular solve, it has not been clear that triangular solves could be employed usefully in programs written for massively parallel architectures.

This thesis investigates the problem of statically assigning the tasks of applications represented by repetitive task graphs (such as sonar or radar signal processing) to the processors of a distributed memory multiprocessor system with the objective of maximizing graph instance throughput. The repetitive nature of these task graphs allows for pipelining and the overlapping of successive graph instances, suggesting a departure from classical directed acyclic graph scheduling techniques. To investigate such a claim, a version of the Mapping Heuristic (MH) ELR 90 is extended for use with iterative applications. Then a new heuristic, Periodic Scheduling (PS), is developed to capitalize on the repetitive nature of these task graphs by overlapping successive graph instances. The PS heuristic assigns tasks to processors in such a way so as to minimize the maximal utilization of the processors and the communications links between them. This maximal utilization figure dictates the interval between successive instances of the task graph. We conduct experiments in which the graph instance throughput of PS is compared to that of MH across a broad range of processor topologies, utilizing several communications/computation ratios. It is shown that, compared to MH, the PS heuristic improves the throughput performance between two and 50 percent. Particularly noteworthy improvement is noted on systems with high average inter-node communications costs. Assignment, Distributed processors, Heuristic algorithm, Mapping problem, Scheduling.

19 p. 28 cm

Software tends to misbehave more often than we would like due to bugs and security attacks. The good news is that there are a variety of dynamic program monitoring tools (which we call 'lifeguards') that can detect and sometimes repair these problems at runtime. The bad news, however, is that these lifeguards (e.g., Valgrind) often slow down execution by an order of magnitude or more, thereby limiting their usefulness. With the emergence of chip multiprocessing as the dominant computing platform, the raw horsepower for performing these monitoring tasks may exist on-chip. In order for the lifeguards to effectively exploit this raw horsepower, however, they need two forms of additional support: the ability to unobtrusively observe the dynamic behavior of the monitored application, and the ability to rewind that application for the sake of repairing a problem. In this joint project that we recently started at Intel Research Pittsburgh and Carnegie Mellon University, we are exploring whether this support can be provided by a single new architectural mechanism: a log that is captured by the hardware, managed by the system, and exposed to the lifeguard software.Our initial results using three diverse lifeguards demonstrate an order-of-magnitude speedup relative to equivalent tools written in Valgrind. Our design also includes a prediction-based compression scheme that reduces the log-related bandwidth and storage requirements by an order of magnitude, to less than one byte per instruction. ©2006 Microsoft Corporation. All rights reserved.

An important problem facing numerous research projects on parallelizing compilers for distributed memory machines is that of automatically determining a suitable data partitioning scheme for a program. Most of the current projects leave this tedious problem almost entirely to the user. In this paper, we present a novel approach to the problem of automatic data partitioning. We introduce the notion of constraints on data distribution, and show how a parallelizing compiler can infer those constraints by looking at the data reference patterns in the source code of the program. We show how these constraints may be combined by the compiler to obtain a complete and consistent picture of the data distribution scheme, one that offers good performance in terms of the overall execution time. We illustrate our approach on an example routine, TRED2, from the EISPACK library, to demonstrate its applicability to real programs. Finally, we discuss briefly some other approaches that have recently been proposed for this problem, and argue why ours seems to be more general and powerful.

A major problem in achieving significant speed-up on parallel machines is the overhead involved with synchronizing the concurrent processes. Removing the synchronization constraint has the potential of speeding up the computation. We present asynchronous (AS) and corrected-asynchronous (CA) finite difference schemes for the multi-dimensional heat equation. Although our discussion concentrates on the Euler scheme for the solution of the heat equation, it has the potential of being extended to other schemes and other parabolic partial differential equations. These schemes are analyzed and implemented on the shared memory multi-user Sequent Balance machine . Numerical results for one and two dimensional problems are presented. It is shown experimentally that synchronization penalty can be about 50% of run time: in most cases, the asynchronous scheme runs twice as fast as the parallel synchronous scheme. In general, the efficiency of the parallel schemes increases with processor load, with the time-level, and with the problem dimension. The efficiency of the AS may reach 90% and over, but it provides accurate results only for steady-state values. The CA, on the other hand, is less efficient but provides more accurate results for intermediate (non steady-state) values.

Current electrical systems are faced with the limitation in performance by the electrical interconnect technology determining overall processing speed. In addition, the electrical interconnects containing many long distance interconnects require high power to drive. One of the best methods to overcome these bottlenecks is through the use of optical interconnect to limit interconnect latency and power. This report describes development of Computer Aided Design (CAD) tools for optimizing a new approach to high performance System-on-Chip (SoC) utilizing free-space optical interconnects technology. Two approaches to design and optimization of the optoelectronic systems using optical interconnections are presented.

A major problem in achieving significant speed-up on parallel machines is the overhead involved with synchronizing the concurrent process. Removing the synchronization constraint has the potential of speeding up the computation. The authors present asynchronous (AS) and corrected-asynchronous (CA) finite difference schemes for the multi-dimensional heat equation. Although the discussion concentrates on the Euler scheme for the solution of the heat equation, it has the potential for being extended to other schemes and other parabolic partial differential equations (PDEs). These schemes are analyzed and implemented on the shared memory multi-user Sequent Balance machine. Numerical results for one and two dimensional problems are presented. It is shown experimentally that the synchronization penalty can be about 50 percent of run time: in most cases, the asynchronous scheme runs twice as fast as the parallel synchronous scheme. In general, the efficiency of the parallel schemes increases with processor load, with the time level, and with the problem dimension. The efficiency of the AS may reach 90 percent and over, but it provides accurate results only for steady-state values. The CA, on the other hand, is less efficient, but provides more accurate results for intermediate (non steady-state) values.

16 p. 28 cm

One common cause of poor performance in large-scale shared-memory multiprocessors is limited memory or interconnection network bandwidth.

This paper proposes a few lower bounds for communication complexity of the Gaussian Elimination algorithm on multiprocessors. Three types of architectures are considered: a bus architecture, a nearest neighbor ring network and a nearest neighbor grid network. Additional keywords: Computations, and Grids.

A logical classification of multiprocessor structures from the point of view of control applications is presented. A computation of the response time distribution for a canonical model of a real time multiprocessor is presented. The multiprocessor is approximated by a blocking model. Two separate models are derived: one created from the system's point of view, and the other from the point of view of an incoming task.

This paper attempts to identify some of the central concepts, issues, and challenges that are emerging in the development of imperative, data parallel programming languages for distributed memory multiprocessors. It first describes a common paradigm for such languages that appears to be emerging. The key elements of this paradigm are the specification of distributed data structures, the specification of a virtual parallel computer, and the use of some model of parallel computation and communication. The paper illustrates these concepts briefly with the DINO programming language. Then it discusses some key research issues associated with each element of the paradigm. The most interesting aspect is the model of parallel computation and communication, where there is a considerable diversity of approaches. The paper proposes a new categorization for these approaches, and discusses the relative advantages of disadvantages of the different models.

Embedded systems are distinguished from general-purpose computers in that they consist of special-purpose hardware and software optimized for a specific task. They are pervasive in Army systems, appearing in soldier radios, sensor systems, vehicle control, communication systems, and many other applications. This paper focuses on multiprocessor embedded systems targeted towards signal, image, and video processing applications requiring large computing power and having real-time performance requirements. As transistor sizes shrink, interconnects represent a significant bottleneck for embedded systems designers. Several groups are researching optical interconnects to cope with this trend. Optical interconnects enable new system architectures. These new architectures in turn require new methods for high-level application mapping and hardware/software co-design. In this presentation, we discuss high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessors. We focus on designs that are streamlined for one or more digital signal processing (DSP) applications. That is, we seek to synthesize an application specific interconnect topology for a multiprocessor DSP design. We show that flexible interconnect topologies that allow single-hop communication between processors offer advantages for reduced power and latency.

Consider the problem of scheduling a taskset on a multiprocessor so that all deadlines are met. Assume (i) constrained-deadline sporadic tasks, i.e., a task generates a sequence of jobs and the deadline of a job is no greater than the minimum inter-arrival time of the task that generates the job, (ii) stage-parallelism, i.e., a task comprises one or more stages with a stage comprising one or many segments so that segments in the same stage are allowed to execute in parallel and a segment is allowed to execute only if all segments of the previous stage have finished, (iii) two-type heterogeneous multiprocessor platform, i.e., there are processors of two types, type-1 and type- 2, and for each task, there is a specification of its execution speed on a type-1 processor and on a type-2 processor, and (iv) intratype migration, i.e., a job can migrate between processors of the same type but for a task, all jobs of this task must execute on the same processor type. We present an algorithm for this problem; it assigns each task to a processor type and then schedules tasks on processors of each type with global-Earliest-Deadline-First. This algorithm has pseudo-polynomial time complexity and speedup factor at most 5. This is the first algorithm for scheduling parallel real-time tasks on a heterogeneous multiprocessor with provably good performance.

Effective use of large-scale multiprocessors requires the elimination of all bottlenecks that reduce processor utilization. One such bottleneck is memory contention. In this paper we show that memory contention occurs in many parallel applications, when those applications are run on large-scale shared- memory multiprocessors. In our simulations of several parallel applications on a large-scale machine, we observed that some applications exhibit near-perfect speedup on hundreds of processors when the effect of memory contention is ignored, and exhibit no speedup at all when memory contention is considered. As the number of processors is increased, many applications exhibit an increase in both the number of hot spots and in the degree of contention for each hot spot. In addition, we observed that hot spots are spread throughout memory for some applications, and that eliminating hot spots on an individual basis can cause other hot spots to worsen. These observations suggest that modern multiprocessors require some mechanism to alleviate hot-spot contention. We evaluate the effectiveness of two different mechanisms for dealing with hot-spot contention in direct-connected, distributed-shared-memory multiprocessors: queueing requests at the memory module, which allows a memory module to be more highly utilized during periods of contention, and increasing the effective bandwidth to memory by having the coherency protocol distribute the hot data to multiple memory modules. We show that queueing requires long queues at each memory module, and does not perform as well as our proposed coherency protocol, which essentially eliminates memory contention in the applications we consider. Memory contention, Hot spots, Eager combining, Coherency protocols

Nearly 40 scientists from 9 countries outside Russia attended the conference. The countries supplying the most participants were France, Britain, and the United States. They were joined by a rotating collection of about 80 Russian scientists affiliated with the ten institutes ot the Russian Academy ot Science (RAS) which provided speakers tor the conference. Russian speakers came from institutes of RAS in Moscow, Nevosibirsk, St. Petersburg, and the Ukraine. The conference was beneficial for all. The visiting western scientists were given access to some of the latest Russian developments in the technologies for parallel computer programming met Russian scientists that had participated in legendary projects such as BESM and MARS, and could make or renew acquaintances with leaders of the Russian research institutes that are just coming into the world market as reliable providers of inexpensively priced, high quality computer systems software. They also had free access to the many cultural treasures of Moscow and could see Russian society firsthand in the transition between centrally controlled and individually directed economies. The Russians were given badly needed opportunities to meet western corporate and academic computer scientists with which they must seen term economic and scientific alliances it they are to survive personally and professionally. (KAR) P. 1

DokuWiki: Programming Massively Parallel Multiprocessors with CUDA Dumped with DokuWiki-Dumper v0.1.44, and uploaded with dokuWikiUploader v0.1.44.

A heterogeneous shared memory multiprocessor, which contains different types of specialized processors, may execute a complex problem faster than either a homogeneous multiprocessor or a heterogeneous network. However, since dissimilar processors often use different representations for primitive data types, the shared data must be transformed. Analytical performance models and queueing models predict the performance advantages are provided by hardware transformation units, caching of unshared data, and local memory. Conversely, caching of shared data and the location of the transformation units have a less significant effect on performance. The primary applications for these type of designs are in special purpose applications which require maximum performance and tight coupling between heterogeneous processors. The linking that must be done at compile time makes these designs less suited for general purpose applications and development work.

The design, implementation, and performance evaluation of a message passing facility (MPF) for shared memory multiprocessors are presented. The MPF is based on a message passing model conceptually similar to conversations. Participants (parallel processors) can enter or leave a conversation at any time. The message passing primitives for this model are implemented as a portable library of C function calls. The MPF is currently operational on a Sequent Balance 21000, and several parallel applications were developed and tested. Several simple benchmark programs are presented to establish interprocess communication performance for common patterns of interprocess communication. Finally, performance figures are presented for two parallel applications, linear systems solution, and iterative solution of partial differential equations.

Many CFD (computational fluid dynamics) and other scientific applications can be partitioned into subproblems. However, in general the partitioned subproblems are very large. They demand high performance computing power themselves, and the solutions of the subproblems have to be combined at each time step. In this paper, the cubeconnect cube (CCCube) architecture is studied. The CCCube architecture is an extended hypercube structure with each node represented as a cube. It requires fewer physical links between nodes than the hypercube, and provides the same communication support as the hypercube does on many applications. The reduced physical links can be used to enhance the bandwidth of the remanding links and, therefore, enhance the overall performance. The concept and the method to obtain optimal CCCubes, which are the CCCubes with a minimum number of links under a given total number of nodes, are proposed. The superiority of optimal CCCubes over standard hypercubes has also been shown in terms of the link usage in the embedding of a binomial tree. A useful computation structure based on a semi-binomial tree for divide-and- conquer type of parallel algorithms has been identified. We have shown that this structure can be implemented in optimal CCCubes without performance degradation compared with regular hypercubes. The result presented in this paper should provide a useful approach to design of scientific parallel computers.... Parallel processing, Parallel architectures, Hypercube, Cubeconnected cube, Optimal cube-connected cube, Divide-and-conquer paradigm, CFD applications.

We conduct a detailed study of the performance effects of irregular communications patterns on the CM-2. We characterized the communications capabilities of the CM-2 under a variety of controlled conditions. In the process of carrying out our performance evaluation, we develop and make extensive use of a parameterized synthetic mesh. In addition we carry out timings with unstructured meshes generated for aerodynamic codes and a set of sparse matrices with banded patterns of non-zeros. This benchmarking suite stresses the communications capabilities of the CM-2 in a range of different ways. Our benchmark results demonstrate that it is possible to make effective use of much of the massive concurrency available in the communications network.

This report outlines an approach to a methodology for evaluating high performance, reliable computers. The purpose of the methodology is to provide a framework and a basis for tool development that will make it possible to conduct such evaluations systematically and efficiently. The increasing complexities of high performance computer systems and the stringent requirement for high reliability in harsh environments (e.g., space) make such an evaluation methodology an absolute necessity. The report discusses sources of difficulty in evaluation, such as the many complexities of multiprocessing, the difficulty of distinguishing various factor (algorithms, software), operating systems, fault diagnostics, etc.) that affect performance and fault tolerance, the use of formal and experimental analyses, and the special problems of computer security. Criteria and suggestions are given for the design of unified working environments and specific classes of tools that support the methodology.

Exploiting full computational power of current more and more hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-uniform architecture. Unfortunately, most operating systems only provide a poor scheduling API that does not allow applications to transmit valuable scheduling hints to the system. In a previous paper, we showed that using a bubble-based thread scheduler can significantly improve applications' performance in a portable way. However, since multithreaded applications have various scheduling requirements, there is no universal scheduler that could meet all these needs. In this paper, we present a framework that allows scheduling experts to implement and experiment with customized thread schedulers. It provides a powerful API for dynamically distributing bubbles among the machine in a high-level, portable, and efficient way. Several examples show how experts can then develop, debug and tune their own portable bubble schedulers.

The FITS is the standard file format in astronomy, and it has been extended to agree with astronomical needs of the day. However, astronomical datasets have been inflating year by year. In case of ALMA telescope, a ~ TB scale 4-dimensional data cube may be produced for one target. Considering that typical Internet bandwidth is a few 10 MB/s at most, the original data cubes in FITS format are hosted on a VO server, and the region which a user is interested in should be cut out and transferred to the user (Eguchi et al., 2012). The system will equip a very high-speed disk array to process a TB scale data cube in a few 10 seconds, and disk I/O speed, endian conversion and data processing one will be comparable. Hence to reduce the endian conversion time is one of issues to realize our system. In this paper, I introduce a technique named "just-in-time endian conversion", which delays the endian conversion for each pixel just before it is really needed, to sweep out the endian conversion time; by applying this method, the FITS processing speed increases 20% for single threading, and 40% for multi-threading compared to CFITSIO. The speed-up by the method tightly relates to modern CPU architecture to improve the efficiency of instruction pipelines due to break of "causality", a programmed instruction code sequence.

Heterogeneous multicore architectures are becoming increasingly popular due to their potential of achieving high performance and energy efficiency compared to the homogeneous multicore architectures. In such systems, the real-time scheduling problem becomes more challenging in that processors have different speeds. A job executing on a processor with speed $x$ for $t$ time units completes $(x \cdot t)$ units of execution. Prior research on heterogeneous multiprocessor real-time scheduling has focused on hard real-time systems, where, significant processing capacity may have to be sacrificed in the worst-case to ensure that all deadlines are met. As meeting hard deadlines is overkill for many soft real-time systems in practice, this paper shows that on soft real-time heterogeneous multiprocessors, bounded response times can be ensured for globally-scheduled sporadic task systems with no utilization loss. A GEDF-based scheduling algorithm, namely GEDF-H, is presented and response time bounds are established under both preemptive and non-preemptive GEDF-H scheduling. Extensive experiments show that the magnitude of the derived response time bound is reasonable, often smaller than three task periods. To the best of our knowledge, this paper is the first to show that soft real-time sporadic task systems can be supported on heterogeneous multiprocessors without utilization loss, and with reasonable predicted response time.