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This thesis investigates the problem of statically assigning the tasks of applications represented by repetitive task graphs (such as sonar or radar signal processing) to the processors of a distributed memory multiprocessor system with the objective of maximizing graph instance throughput. The repetitive nature of these task graphs allows for pipelining and the overlapping of successive graph instances, suggesting a departure from classical directed acyclic graph scheduling techniques. To investigate such a claim, a version of the Mapping Heuristic (MH) [ELR 90] is extended for use with iterative applications. Then a new heuristic, Periodic Scheduling (PS), is developed to capitalize on the repetitive nature of these task graphs by overlapping successive graph instances. The PS heuristic assigns tasks to processors in such a way so as to minimize the maximal utilization of the processors and the communications links between them. This maximal utilization figure dictates the interval between successive instances of the task graph. We conduct experiments in which the graph instance throughput of PS is compared to that of MH across a broad range of processor topologies, utilizing several communications/computation ratios. It is shown that, compared to MH, the PS heuristic improves the throughput perfonnance between two and 50 percent Particularly noteworthy improvement is noted on systems with high average inter-node communications costs.

Many of the issues in developing an efficient interface for communication on distributed memory machines are described and a portable interface is proposed. Although the hardware component of message latency is less than one microsecond on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 microseconds. The reason for this imbalance is that the software interface does not match the hardware. By changing the interface to match the hardware more closely, applications with fine grained communication can be put on these machines. Based on several tests that were run on the iPSC/860, an interface that will better match current distributed memory machines is proposed. The model used in the proposed interface consists of a computation processor and a communication processor on each node. Communication between these processors and other nodes in the system is done through a buffered network. Information that is transmitted is either data or procedures to be executed on the remote processor. The dual processor system is better suited for efficiently handling asynchronous communications compared to a single processor system. The ability to send data or procedure is very flexible for minimizing message latency, based on the type of communication being performed. The test performed and the proposed interface are described.

Many CFD (computational fluid dynamics) and other scientific applications can be partitioned into subproblems. However, in general the partitioned subproblems are very large. They demand high performance computing power themselves, and the solutions of the subproblems have to be combined at each time step. In this paper, the cubeconnect cube (CCCube) architecture is studied. The CCCube architecture is an extended hypercube structure with each node represented as a cube. It requires fewer physical links between nodes than the hypercube, and provides the same communication support as the hypercube does on many applications. The reduced physical links can be used to enhance the bandwidth of the remanding links and, therefore, enhance the overall performance. The concept and the method to obtain optimal CCCubes, which are the CCCubes with a minimum number of links under a given total number of nodes, are proposed. The superiority of optimal CCCubes over standard hypercubes has also been shown in terms of the link usage in the embedding of a binomial tree. A useful computation structure based on a semi-binomial tree for divide-and- conquer type of parallel algorithms has been identified. We have shown that this structure can be implemented in optimal CCCubes without performance degradation compared with regular hypercubes. The result presented in this paper should provide a useful approach to design of scientific parallel computers.... Parallel processing, Parallel architectures, Hypercube, Cubeconnected cube, Optimal cube-connected cube, Divide-and-conquer paradigm, CFD applications.

Consider the problem of scheduling a taskset on a multiprocessor so that all deadlines are met. Assume (i) constrained-deadline sporadic tasks, i.e., a task generates a sequence of jobs and the deadline of a job is no greater than the minimum inter-arrival time of the task that generates the job, (ii) stage-parallelism, i.e., a task comprises one or more stages with a stage comprising one or many segments so that segments in the same stage are allowed to execute in parallel and a segment is allowed to execute only if all segments of the previous stage have finished, (iii) two-type heterogeneous multiprocessor platform, i.e., there are processors of two types, type-1 and type- 2, and for each task, there is a specification of its execution speed on a type-1 processor and on a type-2 processor, and (iv) intratype migration, i.e., a job can migrate between processors of the same type but for a task, all jobs of this task must execute on the same processor type. We present an algorithm for this problem; it assigns each task to a processor type and then schedules tasks on processors of each type with global-Earliest-Deadline-First. This algorithm has pseudo-polynomial time complexity and speedup factor at most 5. This is the first algorithm for scheduling parallel real-time tasks on a heterogeneous multiprocessor with provably good performance.

As multiprocessing becomes increasingly successful in scientific and commercial computing, parallel systems will be subjected to increasingly complex and challenging workloads. To ensure good job response and high resource utilization, algorithms are needed to allocate resources to jobs and to schedule the jobs. The focus of this thesis is in between the theory and practice of scheduling: it includes modeling, performance analysis and practical algorithmic. We present a variety of new techniques for scheduling problems relevant to parallel scientific computing. The thesis progresses from new compile-time algorithms for message scheduling through new runtime algorithms for processor scheduling to a unified framework for allocating multiprocessor resources to competing jobs while optimizing both individual application performance and system throughput. The compiler algorithm schedules network communication for parallel programs accessing distributed arrays. By analyzing and optimizing communication patterns globally, we often reduce communication costs by factors of two to three in an implementation based on IBM's High-Performance Fortran compiler. The best parallelizing compilers at present support regular, static, array-based parallelism. But parallel programmers are out-growing this model. Many scientific and commercial applications have a two-level structure: the outer level is a potentially irregular and dynamic task graph, and the inner level comprises relatively regular parallelism within each task. We give new runtime algorithms for allocating processors to such tasks.

As multiprocessing becomes increasingly successful in scientific and commercial computing, parallel systems will be subjected to increasingly complex and challenging workloads. To ensure good job response and high resource utilization, algorithms are needed to allocate resources to jobs and to schedule the jobs. The focus of this thesis is in between the theory and practice of scheduling: it includes modeling, performance analysis and practical algorithmic. We present a variety of new techniques for scheduling problems relevant to parallel scientific computing. The thesis progresses from new compile-time algorithms for message scheduling through new runtime algorithms for processor scheduling to a unified framework for allocating multiprocessor resources to competing jobs while optimizing both individual application performance and system throughput. The compiler algorithm schedules network communication for parallel programs accessing distributed arrays. By analyzing and optimizing communication patterns globally, we often reduce communication costs by factors of two to three in an implementation based on IBM's High-Performance Fortran compiler. The best parallelizing compilers at present support regular, static, array-based parallelism. But parallel programmers are out-growing this model. Many scientific and commercial applications have a two-level structure: the outer level is a potentially irregular and dynamic task graph, and the inner level comprises relatively regular parallelism within each task. We give new runtime algorithms for allocating processors to such tasks.

System reliability is an important issue in designing modern multiprocessor systems. This paper proposes a fault-tolerant, scalable, multiprocessor system architecture that adopts a pipeline scheme. To verify the performance of the proposed system, the SimEvent/Stateflow tool of the MATLAB program was used to simulate the system. The proposed system uses twelve processors (P), connected in a linear array, to build a ten-stage system with two backup processors (BP). However, the system can be expanded by adding more processors to increase pipeline stages and performance, and more backup processors to increase system reliability. The system can automatically reorganize itself in the event of a failure of one or two processors and execution continues without interruption. Each processor communicates with its neighboring processors through input/output (I/O) ports which are used as bypass links between the processors. In the event of a processor failure, the function of the faulty processor is assigned to the next processor that is free from faults. The fast Fourier transform (FFT) algorithm is implemented on the simulated circuit to evaluate the performance of the proposed system. The results showed that the system can continue to execute even if one or two processors fail without a noticeable decrease in performance.

The Spring project has been very active in multiple areas of real-time computing. We have developed significant results in many aspects of real-time scheduling, in real-time operating system design, in real-time transactions, and in time constrained communication protocols. We have also made progress in implementing a software (simulation) testbed, in developing a hardware operating system kernel testbed called SpringNet, and in implementing real-time transactions on a hardware testbed called CARAT. We have also begun a substantial research effort concerning dependable real-time systems. In the following sections we provide a brief overview of the status and plans for the Spring project as a whole.

The need for computing power has forced a migration from serial computation on a single processor to parallel processing on multiprocessor architectures. However, without effective means to monitor (and visualize) program execution, debugging, and tuning parallel programs becomes intractably difficult as program complexity increases with the number of processors. Research on performance evaluation tools for multiprocessors is being carried out at ARC. Besides investigating new techniques for instrumenting, monitoring, and presenting the state of parallel program execution in a coherent and user-friendly manner, prototypes of software tools are being incorporated into the run-time environments of various hardware testbeds to evaluate their impact on user productivity. Our current tool set, the Ames Instrumentation Systems (AIMS), incorporates features from various software systems developed in academia and industry. The execution of FORTRAN programs on the Intel iPSC/860 can be automatically instrumented and monitored. Performance data collected in this manner can be displayed graphically on workstations supporting X-Windows. We have successfully compared various parallel algorithms for computational fluid dynamics (CFD) applications in collaboration with scientists from the Numerical Aerodynamic Simulation Systems Division. By performing these comparisons, we show that performance monitors and debuggers such as AIMS are practical and can illuminate the complex dynamics that occur within parallel programs.

The design, implementation, and performance evaluation of a message passing facility (MPF) for shared memory multiprocessors are presented. The MPF is based on a message passing model conceptually similar to conversations. Participants (parallel processors) can enter or leave a conversation at any time. The message passing primitives for this model are implemented as a portable library of C function calls. The MPF is currently operational on a Sequent Balance 21000, and several parallel applications were developed and tested. Several simple benchmark programs are presented to establish interprocess communication performance for common patterns of interprocess communication. Finally, performance figures are presented for two parallel applications, linear systems solution, and iterative solution of partial differential equations.

The availability of instruction-level simulators for the CRAY X-MP and the CRAY-2, together with early access to the MFECC and NAS CRAY-2's, has made possible the study of a variety of equation-solving issues for many-processor VMP configurations. These include: (1) the development of equation-solving algorithms on the CRAY-2, and; (2) task granularity studies; and (3) memory conflict studies.

To make shared-memory multiprocessors scalable, researchers are now exploring cache coherence protocols that do not rely on broadcast, but instead send invalidation messages to individual caches that contain stale data. The feasibility of such directory-based protocols is highly sensitive to the cache invalidation patterns that parallel programs exhibit. In this paper, we analyze the cache invalidation patterns caused by several parallel applications and investigate the effect of these patterns on a directory-based protocol. Our results are based on multiprocessor traces with 4, 8 and 16 processors. To get insight into what the invalidation patterns would look like beyond 16 processors, we propose a classification scheme for data objects found in parallel applications and link the invalidation traffic patterns observed in the traces back to these high-level objects. Our results show that synchronization objects have very different invalidation patterns from those of other data objects. A write reference to a synchronization object usually causes invalidations in many more caches. We point out situations where restructuring the application seems appropriate to reduce the invalidation traffic, and others where hardware support is more appropriate. Our results also show that it should be possible to scale 'well-written' parallel programs to a large number of processors without an explosion in invalidation traffic.

22 p. 28 cm

The memory consistency model is a fundamental system property characterizing a multiprocessor. The relative merits of strict versus relaxed memory models have been widely debated in terms of their impact on performance, hardware complexity and programmability. This paper adds a new dimension to this discussion: the impact of memory models on software reliability. By allowing some instructions to reorder, weak memory models may expand the window between critical memory operations. This can increase the chance of an undesirable thread-interleaving, thus allowing an otherwise-unlikely concurrency bug to manifest. To explore this phenomenon, we define and study a probabilistic model of shared-memory parallel programs that takes into account such reordering. We use this model to formally derive bounds on the \emph{vulnerability} to concurrency bugs of different memory models. Our results show that for 2 (or a small constant number of) concurrent threads, weaker memory models do indeed have a higher likelihood of allowing bugs. On the other hand, we show that as the number of parallel threads increases, the gap between the different memory models becomes proportionally insignificant. This suggests the counter-intuitive rule that \emph{as the number of parallel threads in the system increases, the importance of using a strict memory model diminishes}; which potentially has major implications on the choice of memory consistency models in future multi-core systems.

The design, implementation, and performance evaluation of a message passing facility (MPF) for shared memory multiprocessors are presented. The MPF is based on a message passing model conceptually similar to conversations. Participants (parallel processors) can enter or leave a conversation at any time. The message passing primitives for this model are implemented as a portable library of C function calls. The MPF is currently operational on a Sequent Balance 21000, and several parallel applications were developed and tested. Several simple benchmark programs are presented to establish interprocess communication performance for common patterns of interprocess communication. Finally, performance figures are presented for two parallel applications, linear systems solution, and iterative solution of partial differential equations.

Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. This thesis presents the results of the search for a cache coherence solution for Alewife, a large-scale multiprocessor being built at MIT. The research focuses on coherence protocols that use a directory, a list of cached copies of data, to avoid the need for a system-wide broadcast mechanism. The structure and the implementation of a number of coherence schemes are evaluated with coupled and decoupled simulation techniques. In addition to comparing the protocols in terms of hardware overhead and performance, the thesis reports on the experience gained by implementing several different schemes in ASIM, the Alewife machine simulator. The protocol search reaches two major conclusions: First, by using system-level optimizations, it is possible to use caches to build large-scale shared-memory multiprocessors. Second, the Alewife machine should use the integrated systems approach -- handling common cases in hardware and exceptional cases in software -- to solve the cache coherence problem.

The memory organization and technological design parameters which create memory access conflicts and affect performance of the CRAY family of processors are studied. Measurements on the dynamic-memory CRAY-2 system are presented.

Traditionally, symmetric multiprocessors have used modest numbers of processors. Since many of them were bus-based systems, they inherently lacked scalability to what might be referred to as moderate-sized systems. With the advent of the Sun HPC 10000 and the SGI Origin, we now have symmetric multiprocessors that have successfully scaled to moderate-sized systems. In fact, SGI has had some success at scaling the Origin into the lower end of the range of large systems. The first symmetric multiprocessor to make that claim was the Convex Exemplar. But based on our experience at the Distributed Center located at NRAD, San Diego, CA (now the Naval Command Control and Ocean Surveillance Center), its overall performance and scalability left something to be desired. This report presents the results from runs involving a variety of programs on the 561 Origins and Sun HPC 10000s located at the U.S. Army Research Laboratory (ARL)-MSRC, the Naval Research Laboratory (NRL-DC), Washington, DC, and other places. Some of these codes (e.g., F3D) are shared memory codes using OPENMP or its predecessors. The remaining codes use message passing (mostly MPI, but one PVM code was tested as well). Additionally, a limited number of runs were made with the CTH code when using processors on more than one Sun HPC 10000. While most of these codes ran well, some codes did require modifications. Additionally, in the process of making these measurements, the authors gained useful insights as to what does and does not work well on these systems.

Inexpensive multiprocessor systems that obtain notable improvement in performance over sequential processors are currently under development at U.C. Berkeley. We are describing a crossbar system, an interconnection network, as a component of a multiprocessor system that may be used for experimentation with different processor architectures. For instance, one may wish to experiment with (1) interconnecting computing modes, which contain processors, memory, and caches and (2) connecting processors to memory modules in a dance hall configuration. The crossbar system is based on single bit-slice 16x16 crossbar chip with low latency, i.e., less than 50ns of delay using a 2 micron static CMOS technology. The chip is designed so that it can be implemented in CMOS or EDFL GaAs. We used three different tools to develop this chip: (1) Lager Tools, (2) NCR and Mentor Graphics tools, and (3) Timberwolfe standard-cell tools. By stacking 33 of these chips, a crossbar system has been designed that interconnects sixteen processing elements (PE) for transferring 32 bits of data and address with one-cycle read/write capability, providing there is no contention between PEs. If a conflict occurs, a tree arbiter impartially selects a PE. A printed circuit board (PCB) version of the crossbar system has also been designed. This multilayer PCB acts as a backplane and contains the crossbar chips on one side and VME connectors to the PEs on the other side.

Multi-core processors support all modern electronic devices nowadays. However, temperature and performance management are one of the most critical issues in the design of today’s microprocessors. In this paper, we propose a framework by using an optimal control method based on fan speed and frequency control of the multi-core processor. The goal is to optimize performance and at the same time avoid violating an expected temperature. Our proposed method uses a high-precision thermal and power model for multi-core processors. This method is validated on asymmetric ODROID-XU4 multi-core processor. The experimental results show the ability of the proposed method to achieve the adequate trade-off between performance and temperature control.

Software tends to misbehave more often than we would like due to bugs and security attacks. The good news is that there are a variety of dynamic program monitoring tools (which we call 'lifeguards') that can detect and sometimes repair these problems at runtime. The bad news, however, is that these lifeguards (e.g., Valgrind) often slow down execution by an order of magnitude or more, thereby limiting their usefulness. With the emergence of chip multiprocessing as the dominant computing platform, the raw horsepower for performing these monitoring tasks may exist on-chip. In order for the lifeguards to effectively exploit this raw horsepower, however, they need two forms of additional support: the ability to unobtrusively observe the dynamic behavior of the monitored application, and the ability to rewind that application for the sake of repairing a problem. In this joint project that we recently started at Intel Research Pittsburgh and Carnegie Mellon University, we are exploring whether this support can be provided by a single new architectural mechanism: a log that is captured by the hardware, managed by the system, and exposed to the lifeguard software.Our initial results using three diverse lifeguards demonstrate an order-of-magnitude speedup relative to equivalent tools written in Valgrind. Our design also includes a prediction-based compression scheme that reduces the log-related bandwidth and storage requirements by an order of magnitude, to less than one byte per instruction. ©2006 Microsoft Corporation. All rights reserved.

It is currently possible to build multiprocessor systems which will support the tightly coupled activity of hundreds to thousands of different instruction streams, or processes. This can be done by coupling many monoprocessors, or a smaller number of pipelined multiprocessors, through a high concurrency switching network. The switching network may be couple processors to memory modules, resulting in a shared memory multiprocessor system, or it may couple processor/memory pairs, resulting in a distributed memory system. The need to direct the activity of very many processes simultaneously places qualitatively different demands on a programming language than the direction of a single process. In spite of the different requirements, most languages for multiprocessors have been simple extensions of conventional, single stream programming languages. The extensions are often implemented by way of subroutine calls and have little impact on the basic structure of the language. This paper attempts to examine the underlying conceptual structure of parallel languages for large scale multiprocessors on the basis of an existing language for shared memory multiprocessors, known as the Force, and to extend the concepts in this language to distributed memory systems.

Consider the problem of scheduling a taskset on a multiprocessor to meet all deadlines. Assume (i) constrained deadline sporadic tasks, i.e., a task generates a sequence of jobs and the deadline of a job is no greater than the minim minter-arrival time of the task that generates the job, (ii) stage parallelism, i.e., a task comprises one or more stages with a stage comprising one or many segments so that segments in the same stage are allowed to execute in parallel and a segment is allowed to execute only if all segments of the previous stage have finished, (iii) two-type heterogeneous multiprocessor platform, i.e., there are processors of two types, type-1 and type-2, and for each task, there is a specification of its execution speed on a type-1 processor and on a type-2 processor, and (iv) intratype migration, i.e., a job can migrate between processors of the same type but for a task, all jobs of this task must execute on the same processor type. We present an algorithm for this problem; it assigns each task to a processor type and then schedules tasks on processors of each type with global-Earliest-Deadline-First. It has pseudo-polynomial time complexity and in our evaluation with randomly-generated task sets with systems up to 256 tasks and 256 processors, the algorithm never took more than 2.5 seconds to finish. We show that the speedup factor of the algorithm is most 5. This is the first algorithm for scheduling parallel real-time tasks on a heterogeneous multiprocessor with provably good performance.

This report summarizes the activities supported by DOD contract N00014-81-C-2151 (ARPA order number 4095) and the results of those activities. The period of this contract was originally scheduled to be from 80 Dec 19 through 81 Dec 19 but it was extended by a no-cost extension until 82 Jan 19. It was succeeded by DOD contract N00014-82-C-2087 (ARP order number 4095) which supports a continuation of research activities in the same area. We view the former contact as supporting a pilot project, initiating a research program that is still under way. For this reason, the following pages will have more of the flavor of a interim report than a final summation.

19 p. 28 cm

Large-scale shared-memory multiprocessors such as the BBN Butterfly and IBM RP3 introduce a new level in the memory hierarchy; multiple physical memories with different memory access times. An operating system for these NUMA (NonUniform Memory Access) multiprocessors should provide traditional virtual memory management, facilitate dynamic and widespread memory sharing, and minimize the apparent disparity between local and nonlocal memory. In addition, the implementation must be scalable to configurations with hundreds or thousands of processors. This paper describes memory management in the Psyche multiprocessor operating system, under development at the University of Rochester. The Psyche kernel manages a multi-level memory hierarchy consisting of local memory, nonlocal memory, and backing store. Local memory stores private data and serves as a cache for shared data; nonlocal memory stores shared data and serves as a disk cache. The system structure isolates the policies and mechanisms that manage different layers in the memory hierarchy, so that customized data structures and policies can be constructed for each layer. Local memory management policies are implemented using mechanisms that are independent of the architectural configuration; global policies are implemented using multiple processes that increase in number as the architecture scales. Psyche currently runs on the BBN Butterfly Plus multiprocessor. (kr)

We propose a few implementations of the Alternating Direction Method for solving parabolic partial differential equations on multiprocessors. A careful complexity analysis of these implementations shows that, contrary to what is generally believed, the method can be made highly efficient on parallel architectures by using pipelining and variations of the classical Gaussian elimination algorithm for solving tridiagonal systems.

A detailed study of the performance effects of irregular communications patterns on the CM-2 was conducted. The communications capabilities of the CM-2 were characterized under a variety of controlled conditions. In the process of carrying out the performance evaluation, extensive use was made of a parameterized synthetic mesh. In addition, timings with unstructured meshes generated for aerodynamic codes and a set of sparse matrices with banded patterns on non-zeroes were performed. This benchmarking suite stresses the communications capabilities of the CM-2 in a range of different ways. Benchmark results demonstrate that it is possible to make effective use of much of the massive concurrency available in the communications network.

An important architectural design decision affecting the performance of coherent caches in shared-memory multiprocessors is the choice of block size. There are two primary factors that influence this choice: the reference behavior of application programs and the remote access bandwidth and latency of the machine. Several studies have shown that increasing the block size can lower the miss rate and reduce the number of invalidations. However, increasing the block size can also increase the miss rate by, for example, increasing false sharing or the number of cache evictions. Large cache blocks can also generate network contention. Given that we anticipate enormous increases in both network bandwidth and latency in large-scale, shared-memory multiprocessors, the question arises as to what effect these increases will have on the choice of block size. We use analytical modeling and execution-driven simulation of parallel programs on a large-scale shared-memory machine to examine the relationship between cache block size and application performance as a function of remote access bandwidth and latency. We show that even under assumptions of high remote access bandwidth, the best application performance usually results from using cache blocks between 32 and 128 bytes in size.

Given standard characteristics of processors and memory, we present two simple ways of estimating the performance of shared memory multiprocessors. At the cost of a few simple arithmetic operations, a computer designer can estimate the range of performance using our 4-point bound model. If more accuracy is required, we show that a one page program can estimate performance within 3% of trace-driven simulation, while reducing software development time, disk space, and CPU time by orders of magnitude. To demonstrate the use of our models, an application to the SPUR multiprocessor design is presented.

There are at least two-critical components required to obtain extremely fast methods for solving sparse linear systems. One is the use of efficient and robust numerical algorithms, and the other is the employment of effective techniques for delivering a large amount of computing power. These requirements can conflict with one another in a variety of ways. Many modern methods of solving reasonably general classes of linear systems involve a degree of implicitness; this implicitness can limit the amount of available concurrency. When Krylov space linear solvers are used, the choice of preconditioner can play a major role in determining the operation count of the resulting algorithm. Unfortunately, some of the most powerful preconditioners are obtained by using incompletely factored matrices. To apply these preconditioners, we must repeatedly solve sparse triangular systems. The efficiency with which such solutions could be carried out was characterized by Saad and Schultz. Sparse triangular systems arising from a range of problems have been solved efficiently on a number of shared memory architectures 1,3,4,9. Because data dependencies limit the concurrency available from a sparse triangular solve, it has not been clear that triangular solves could be employed usefully in programs written for massively parallel architectures.

Exploiting the performance potential of distributed memory machines requires a careful distribution of data across the processors. Vienna Fortran is a language extension of Fortran which provides the user with a wide range of facilities for such mapping of data structures. However, programs in Vienna Fortran are written using global data references. Thus, the user has the advantages of a shared memory programming paradigm while explicitly controlling the placement of data. In this paper, we present the basic features of Vienna Fortran along with a set of examples illustrating the use of these features.

Cache coherence protocols for shared-memory multiprocessors use invalidations or updates to maintain coherence across processors. Although invalidation protocols usually produce higher miss rates, update protocols typically perform worse. Detailed simulations of these two classes of protocol show that the excessive network traffic caused by update protocols significantly degrades performance, even with infinite bandwidth. Motivated by this observation, we categorize the coherence traffic in update-based protocols and show that, for most applications, more than 90% of all updates generated by the protocol are unnecessary. We identify application characteristics that generate useless update traffic, and compare the isolated and combined effects of several software and hardware techniques for eliminating useless updates. These techniques include dynamic and static hybrid protocols, false sharing elimination strategies, and coalescing write buffers. Our simulations show that software caching (where coherence is managed under programmer or compiler control) and the dynamic hybrid protocol reduce useless updates the most, but coalescing write buffers produce fewer, albeit larger, coherence messages. As a result, coalescing write buffers usually produce the best running time, except when the block size is large or the bandwidth is limited. Finally, based on the observation that the techniques we consider are unable to eliminate a large number of useless updates, we suggest directions for further reducing the useless traffic in update-based protocols.

A validation methodology for testing the performance of fault-tolerant computer systems was developed and applied to the Fault-Tolerant Multiprocessor (FTMP) at NASA-Langley's AIRLAB facility. This methodology was claimed to be general enough to apply to any ultrareliable computer system. The goal of this research was to extend the validation methodology and to demonstrate the robustness of the validation methodology by its more extensive application to NASA's Fault-Tolerant Multiprocessor System (FTMP) and to the Software Implemented Fault-Tolerance (SIFT) Computer System. Furthermore, the performance of these two multiprocessors was compared by conducting similar experiments. An analysis of the results shows high level language instruction execution times for both SIFT and FTMP were consistent and predictable, with SIFT having greater throughput. At the operating system level, FTMP consumes 60% of the throughput for its real-time dispatcher and 5% on fault-handling tasks. In contrast, SIFT consumes 16% of its throughput for the dispatcher, but consumes 66% in fault-handling software overhead.

Software tends to misbehave more often than we would like due to bugs and security attacks. The good news is that there are a variety of dynamic program monitoring tools (which we call 'lifeguards') that can detect and sometimes repair these problems at runtime. The bad news, however, is that these lifeguards (e.g., Valgrind) often slow down execution by an order of magnitude or more, thereby limiting their usefulness. With the emergence of chip multiprocessing as the dominant computing platform, the raw horsepower for performing these monitoring tasks may exist on-chip. In order for the lifeguards to effectively exploit this raw horsepower, however, they need two forms of additional support: the ability to unobtrusively observe the dynamic behavior of the monitored application, and the ability to rewind that application for the sake of repairing a problem. In this joint project that we recently started at Intel Research Pittsburgh and Carnegie Mellon University, we are exploring whether this support can be provided by a single new architectural mechanism: a log that is captured by the hardware, managed by the system, and exposed to the lifeguard software.Our initial results using three diverse lifeguards demonstrate an order-of-magnitude speedup relative to equivalent tools written in Valgrind. Our design also includes a prediction-based compression scheme that reduces the log-related bandwidth and storage requirements by an order of magnitude, to less than one byte per instruction. ©2006 Microsoft Corporation. All rights reserved.

The partitioning of a problem on a domain with unequal work estimates in different subddomains is considered in a way that balances the work load across multiple processors. Such a problem arises for example in solving partial differential equations using an adaptive method that places extra grid points in certain subregions of the domain. A binary decomposition of the domain is used to partition it into rectangles requiring equal computational effort. The communication costs of mapping this partitioning onto different microprocessors: a mesh-connected array, a tree machine and a hypercube is then studied. The communication cost expressions can be used to determine the optimal depth of the above partitioning.

The research of this grant spanned number of topical areas in its four years duration (1) Blocked parallel solution of dense and sparse systems. Closely-related to the original proposal, this research involved a study of the relationship between task granularity and block partitioning size in the solution of linear algebra problems. The rationale for this blocking was the restricted effective memory bandwidth of the shared-memory CRAY-2 due to memory conflicts. The final result was development of unique black-box models of the CRAY-2 memory system based on dedicated machine measurements. In the realization that the limited parallelism of the CRAY-2 was restrictive for future algorithm studies, a new effort precursing future research cooperative with WPAFB personnel was initiated.

An important problem facing numerous research projects on parallelizing compilers for distributed memory machines is that of automatically determining a suitable data partitioning scheme for a program. Most of the current projects leave this tedious problem almost entirely to the user. In this paper, we present a novel approach to the problem of automatic data partitioning. We introduce the notion of constraints on data distribution, and show how a parallelizing compiler can infer those constraints by looking at the data reference patterns in the source code of the program. We show how these constraints may be combined by the compiler to obtain a complete and consistent picture of the data distribution scheme, one that offers good performance in terms of the overall execution time. We illustrate our approach on an example routine, TRED2, from the EISPACK library, to demonstrate its applicability to real programs. Finally, we discuss briefly some other approaches that have recently been proposed for this problem, and argue why ours seems to be more general and powerful.

This paper presents a model to evaluate the performance and overhead of parallelizing sequential code using compiler directives for multiprocessing on distributed shared memory (DSM) systems. With increasing popularity of shared address space architectures, it is essential to understand their performance impact on programs that benefit from shared memory multiprocessing. We present a simple model to characterize the performance of programs that are parallelized using compiler directives for shared memory multiprocessing. We parallelized the sequential implementation of NAS benchmarks using native Fortran77 compiler directives for an Origin2000, which is a DSM system based on a cache-coherent Non Uniform Memory Access (ccNUMA) architecture. We report measurement based performance of these parallelized benchmarks from four perspectives: efficacy of parallelization process; scalability; parallelization overhead; and comparison with hand-parallelized and -optimized version of the same benchmarks. Our results indicate that sequential programs can conveniently be parallelized for DSM systems using compiler directives but realizing performance gains as predicted by the performance model depends primarily on minimizing architecture-specific data locality overhead.

16 p. 28 cm

16 p. 28 cm

This document proposes a few implementation of the Alternating Direction Method for solving parabolic partial differential equations on multiprocessors. A careful complexity analysis of these implementations shows that, contrary to what is generally believed, the method can be made highly efficient on parallel architectures by using pipelining and variations of the classical Gaussian elimination algorithm for solving tridiagonal systems. In an earlier work the authors showed that they could obtain linear speedups for moderate numbers of processors in a ring architecture. This paper discusses extensions to a large number of processors in a 2-D grid architecture and a hypercube.

A class of asynchronous iterative methods is presented for solving a system of equations. Existing iterative methods are identified in terms of asynchronous iterations, and new schemes are introduced corresponding to a parallel implementation on a multiprocessor system with no synchronization between cooperating processes. A sufficient condition is given to guarantee the convergence of any asynchronous iterations, and results are extended to include iterative methods with memory. Asynchronous iterative methods are then evaluated from a computational point of view, and bounds are derived for the efficiency. The bounds are compared with actual measurements obtained by running various asynchronous iterations on a multiprocessor, and the experimental results show clearly the advantage of purely asynchronous iterative methods. (Author)

In article the variant of practical realization of system binaural hearing inherent is offered to the person and many representatives of fauna. Properties binaural hearing are realized by operations above images of the acoustic signals received from a array of microphones. Realization assumes the coherent, synchronized work of 3 microprocessors which are carrying out reading of signals from 4 microphones through two 16 digit ADC with frequency of digitization 100 kHz on each channel with synchronization between channels with accuracy 5 uS. In realized the Flash card in capacity 2 GB and the microprocessor realizing interface USB from the personal COMPUTER is included. Realization provides independent work of system and together with the personal COMPUTER. The system has properties not inherent in hearing of the person – zero time of adaptation at transition from a strong signal to weak and on the contrary, localization of very short signals.

Book Source: Digital Library of India Item 2015.191727 dc.contributor.author: Adarshpal Singh Sethi dc.date.accessioned: 2015-07-08T01:09:06Z dc.date.available: 2015-07-08T01:09:06Z dc.date.digitalpublicationdate: 2005-08-20 dc.identifier.barcode: 1990010090218 dc.identifier.origpath: /rawdataupload/upload/0090/218 dc.identifier.copyno: 1 dc.identifier.uri: http://www.new.dli.ernet.in/handle/2015/191727 dc.description.scannerno: 12 dc.description.scanningcentre: IIIT, Allahabad dc.description.main: 1 dc.description.tagged: 0 dc.description.totalpages: 102 dc.format.mimetype: application/pdf dc.language.iso: English dc.rights: Out_of_copyright dc.source.library: Indian Institute Of Technology Kanpur dc.subject.classification: Technology dc.subject.classification: Engineering. Technology In General dc.subject.classification: Computer Science Engineering dc.title: New Analytic Models For Multiprocessors With Various Interconnection Structures

DokuWiki: Programming Massively Parallel Multiprocessors with CUDA Dumped with DokuWiki-Dumper v0.1.44, and uploaded with dokuWikiUploader v0.1.44.

DokuWiki: Programming Massively Parallel Multiprocessors with CUDA Dumped with DokuWiki-Dumper v0.1.44, and uploaded with dokuWikiUploader v0.1.44.

A general framework for shift register-based test response compressors was developed based on algebraic coding theory. It has advantages over Markov modeling in allowing exact computation of aliasing probability and extension to other forms of built-in self-test. The use of deBruijn graphs was adopted to studies of VLSI-based multiprocessor networks. These allowed derivation of lower bounds on VLSI layout areas and provided a method to meet those bounds. The graphs were extended to hyper-de Bruijn networks. Finally a design was produced for fault-tolerant testable RAM's (TRAM's).

As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectures require new methods for high-level application mapping and hardware/software codesign. In this paper, we present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing applications. That is, we seek to synthesize an application-specific interconnect topology. We show that flexible interconnect topologies utilizing low-hop communication between processors offer advantages for reduced power and latency. We show that existing multiprocessor scheduling algorithms can deadlock if the topology graph is not strongly connected, or if a constraint is imposed on the maximum number of hops allowed for communication. We detail an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock. We show that it is advantageous to perform application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm that utilizes graph isomorphism to pare the design space.