Downloads & Free Reading Options - Results

TRI 1, 2017/2018

TRI 1, 2017/2018

TRI 1, 2017/2018

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on scheduling real-time jobs in a simplified model for cooling and thermal management. A collection of unit-length jobs is given, each job specified by its release time, deadline and heat contribution. If, at some time step, the temperature of the system is t and the processor executes a job with heat contribution h, then the temperature at the next step is (t+h)/2. The temperature cannot exceed the given thermal threshold T. The objective is to maximize the throughput, that is, the number of tasks that meet their deadlines. We prove that, in the offline case, computing the optimum schedule is NP-hard, even if all jobs are released at the same time. In the online case, we show a 2-competitive deterministic algorithm and a matching lower bound.

TRI 3 2016/2017

TRI 3 2016/2017

A thesis by James D. Moore, published spring 1983. There exists in the world of microcomputers a great need to see more of what is “going on" within a particular system. This is often necessary for problem solving, instructional purposes, program design, and even the satisfaction of one's own curiosity. Many programs are also "protected" so that even casual analysis is quite impos- sible. Program step and trace functions are frequently available as software tools but are rendered useless in a great many circumstances by protection schemes. The purpose of this project was to develop a simple and inexpensive hardware device to assist programmers in gaining access to the inner workings of both hardware and software. This device is commonly known as a Bus Rider when found in development system application. Information on this type of hardware is practically non-existent. A literature review revealed only two display-type program aids for microcomputer systems, neither of which alters the processor speed. The Display Board and Bug Lights circuit are useful but rather limited in their ability to display information. Both use a series of discrete LEDs to indicate data, which necessitates a con- stant hexidecimal conversion on the part of the programmer. They are also particular about when and what they display. Microcomputer systems normally perform several hundred thousand operations per second and must. therefore be slowed down a great deal to make any sense of the data transfer at the bus level. This is possible with the 6502 microprocessor because it is an early design and was required to handle the slow memory devices of the time. The device resulting from this project is specifically designed for popular 6502 based microcomputer systems like the Apple II. It consists of a synchronized clock circuit that pulses the Ready Line of the microprocessor and provides variable speed, slow motion, and pause capabilities anywhere within an operating program. A set of six hexadecimal LED displays then decode and display memory locations and the data found in them. A program can be run in "slow motion" and one can actually watch the processor access specific memory locations to transfer data. In essence it allows one to examine, in great detail, the most intimate operations of a microcomputer and its programs.

TRI 1 2017/2018

TRI 1 2017/2018

Trimester 1 2016/2017

Trimester 1 2016/2017

Trimester 1 2016/2017

Trimester 1 2016/2017

Trimester 1 2016/2017

Trimester 1 2016/2017

vii, 349 pages : 24 cm

vii, 349 pages : 24 cm

vii, 349 pages : 24 cm

Includes index

This report consists of two papers that treat reliability of the multiprocessor systems at CMU. The first paper discusses the multiprocessor architectures, reliability features (hardware and software), and measured reliability data. The second paper presents hard failure data from one of the systems, calibrates a hard failure rate model, and analytically models the reliability of the three systems.

This report consists of two papers that treat reliability of the multiprocessor systems at CMU. The first paper discusses the multiprocessor architectures, reliability features (hardware and software), and measured reliability data. The second paper presents hard failure data from one of the systems, calibrates a hard failure rate model, and analytically models the reliability of the three systems.

Recent advances in semiconductor technology have made microprocessor chips and their associated interface and peripheral chips available at low cost and in readily adaptable configurations. The availability of these powerful yet small devices opens up whole new fields of computer control. This project investigated the use of microprocessors and associated hardware to control the heating of a building in order to save energy. A house was simulated on the hybrid computer and controlled by a microprocessor-based digital controller. The microprocessor was a commercially available model, one which could be obtained at low cost and would be accessible to any home owner. By turning the heat off in rooms which were not to be used, a considerable amount of energy could be saved. The program to control the room temperatures would be determined and written on the basis of the probable use of rooms. Tests showed that a significant amount of energy was saved by using the controller, as much as 50%, depending on the use-habits of the house. The house simulation can also be used to study such things as insulation configuration, heater size and location, and room shapes and sizes with respect to the amount of energy saved.

This report documents the implementation of some old and new techniques to the problem of command-and-control signaling within a Category III instrument landing system. The old techniques include the use of tone signaling over balanced lines, along with isolation transformers and gas-discharge elements for lightning protection. The new methods include the application of microprocessor control devices to supervise, format, and interpret all communications. Additional features afforded by the microprocessor approach include automatic and manual maintenance logging at the control tower, more reliable transmission error detection, enhanced system status displays, and a self-contained operator training feature. (Author)

This report documents the implementation of some old and new techniques to the problem of command-and-control signaling within a Category III instrument landing system. The old techniques include the use of tone signaling over balanced lines, along with isolation transformers and gas-discharge elements for lightning protection. The new methods include the application of microprocessor control devices to supervise, format, and interpret all communications. Additional features afforded by the microprocessor approach include automatic and manual maintenance logging at the control tower, more reliable transmission error detection, enhanced system status displays, and a self-contained operator training feature. (Author)

ID-108 Microprocessor floppy disk system - ID Systems Corp

In this report two leading DBMS designs (DBASE II and MDBS III) are evaluated in terms of their design and performance on Altos computer systems. In addition some comments are made on their relative advantages and disadvantages for the average user. The basic conclusions reached are that the relational design of DBASE II is easier to use and apparently performs data manipulation problems better than MDBS III. In large scale applications where reliability and security are imperative, MDBS III is more appropriate since it provides crash recovery, access control, integrity constraints and other key features which DBASE II lacks. (Author)

NPS-PASCAL is a Naval Postgraduate School research project whose goal is the implementation of the PASCAL programming language on a microprocessor-based system. The NPS-PASCAL compiler consists of two software subsystems, the first analyzes the source program and produces a machine-independent intermediate form, while the second produces target machine code. The system is designed to satisfy the constraints of Standard Pascal, as defined by the British Standards Institute/International Standards Organization Working Draft of Standard Pascal.

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

During the last year, several 4.5 in. x 6 in. printed circuit boards have been designed and fabricated for general and special purpose use in prototyping digital circuits. Since these designs represent a considerable effort, this report presents a descriptive overview of the various circuits and printed circuit boards. (Author)

TRI 1 2016/2017

TRI 1 2016/2017

TRI 1 2016/2017

Microprocessor displays - Matrox Electronic Systems LTD. February 1980

Microprocessor displays - Matrox Electronic Systems LTD. February 1980