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Binary phase shift keying is a common modulation method for transmitting binary data because of its superior noise performance. A proposed alternative to the common BPSK receiver is use of three parallel post-detection circuits and majority decision logic to reduce errors, improving the overall performance of the BPSK system. The noise performance of each of two parallel circuits was measured and compared. The first circuit is a conventional BPSK receiver using an integrate and dump circuit. The second circuit incorporates a limiter after the demodulator and prior to the integrate and dump circuit. The conventional circuit is found to provide the same error probability at a 0.2 dB smaller signal to noise ratio. The probability density function of the voltage at various nodes in the post-detection circuits are measured and included in the report along with curves of probability of error versus SNR for the two post-detection circuits.

Binary phase shift keying is a common modulation method for transmitting binary data because of its superior noise performance. A proposed alternative to the common BPSK receiver is use of three parallel post-detection circuits and majority decision logic to reduce errors, improving the overall performance of the BPSK system. The noise performance of each of two parallel circuits was measured and compared. The first circuit is a conventional BPSK receiver using an integrate and dump circuit. The second circuit incorporates a limiter after the demodulator and prior to the integrate and dump circuit. The conventional circuit is found to provide the same error probability at a 0.2 dB smaller signal to noise ratio. The probability density function of the voltage at various nodes in the post-detection circuits are measured and included in the report along with curves of probability of error versus SNR for the two post-detection circuits.

Binary phase shift keying is a common modulation method for transmitting binary data because of its superior noise performance. A proposed alternative to the common BPSK receiver is use of three parallel post-detection circuits and majority decision logic to reduce errors, improving the overall performance of the BPSK system. The noise performance of each of two parallel circuits were measuredand compared. The first circuit is a conventional BPSK receiver using an integrate and dump circuit. The second circuit incorporates a limiter after the demodulator and prior to the integrate and dump circuit. The conventional circuit is found to provide the same error probability at a 0.2 dB smaller signal to noise ratio. The probability density function of the voltage at various nodes in the post-detection circuits are measured and included in the report along with curves of probability of error versus SNR for the two post-detection circuits. Keywords include: BPSK Signaling; Noise Performance; Probability of Error; and Post-Detection Limiter Circuit. (Thesis)