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The Embedded High Performance Scalable Computing Systems (EHPSCS) program is a cooperative agreement between Sanders, A Lockheed Martin Company and DARPA that ran for three years, from Apr 1995 - Apr 1998. The focus of the EHPSCS research program was on the development of a highly integrated, scalable multiprocessing architecture based on leading COTS technologies for environmentally constrained applications. The program developed an 11 GFLOPS embedded processor hardware/software testbed and software development tools to facilitate technology transfer, an advanced packaging insertion approach, and a second generation microarchitecture - the ReConfigurable Transport Engine.

The Embedded High Performance Scalable Computing Systems (EHPSCS) program is a cooperative agreement between Sanders, A Lockheed Martin Company and DARPA that ran for three years, from Apr 1995 - Apr 1998. The focus of the EHPSCS research program was on the development of a highly integrated, scalable multiprocessing architecture based on leading COTS technologies for environmentally constrained applications. The program developed an 11 GFLOPS embedded processor hardware/software testbed and software development tools to facilitate technology transfer, an advanced packaging insertion approach, and a second generation microarchitecture - the ReConfigurable Transport Engine.

Viewgraphs from presentation on the use of streaming and dynamic compilers for high performance embedded computing.

Nowadays, the prevalence of computing systems in our lives is so ubiquitous that we live in a cyber-physical world dominated by computer systems, from pacemakers to cars and airplanes. These systems demand for more computational performance to process large amounts of data from multiple data sources with guaranteed processing times. Actuating outside of the required timing bounds may cause the failure of the system, being vital for systems like planes, cars, business monitoring, e-trading, etc. High-Performance and Time-Predictable Embedded Computing presents recent advances in software architecture and tools to support such complex systems, enabling the design of embedded computing devices which are able to deliver high-performance whilst guaranteeing the application required timing bounds. Technical topics discussed in the book include:  Parallel embedded platforms Programming models Mapping and scheduling of parallel computations Timing and schedulability analysis Runtimes and operating systemsThe work reflected in this book was done in the scope of the European project P SOCRATES, funded under the FP7 framework program of the European Commission. High-performance and time-predictable embedded computing is ideal for personnel in computer/communication/embedded industries as well as academic staff and master/research students in computer science, embedded systems, cyber-physical systems and internet-of-things.

Nowadays, the prevalence of computing systems in our lives is so ubiquitous that we live in a cyber-physical world dominated by computer systems, from pacemakers to cars and airplanes. These systems demand for more computational performance to process large amounts of data from multiple data sources with guaranteed processing times. Actuating outside of the required timing bounds may cause the failure of the system, being vital for systems like planes, cars, business monitoring, e-trading, etc. High-Performance and Time-Predictable Embedded Computing presents recent advances in software architecture and tools to support such complex systems, enabling the design of embedded computing devices which are able to deliver high-performance whilst guaranteeing the application required timing bounds. Technical topics discussed in the book include:  Parallel embedded platforms Programming models Mapping and scheduling of parallel computations Timing and schedulability analysis Runtimes and operating systemsThe work reflected in this book was done in the scope of the European project P SOCRATES, funded under the FP7 framework program of the European Commission. High-performance and time-predictable embedded computing is ideal for personnel in computer/communication/embedded industries as well as academic staff and master/research students in computer science, embedded systems, cyber-physical systems and internet-of-things.

As advancements in CMOS technology trend toward ever increasing core counts in chip multiprocessors for high-performance embedded computing, the discrepancy between on- and off-chip communication bandwidth continues to widen due to the power and spatial constraints of electronic off-chip signalling. Silicon photonics-based communication offers many advantages over electronics for network-on-chip design, namely power consumption that is effectively agnostic to distance traveled at the chip- and board-scale, even across chip boundaries. In this work we develop a design for a photonic network-on-chip with integrated DRAM I/O interfaces and compare its performance to similar electronic solutions using a network-on-chip simulation environment that uniquely captures the physical characteristics of the photonic layer. When used in a circuit-switched network, silicon nanophotonic switches offer higher bandwidth density, low power transmission, and relaxed physical constraints such as pin count and board layout. These effects add up to over 10x better performance and 20-3Ox lower power for projective transform, matrix multiply, and Fast Fourier Transform (FFT), all key algorithms in embedded real-time signal and image processing.

This paper describes a transformational, high-level language approach to High Performance Embedded Computing on the SRC-6 machine and its MAP reconfigurable hardware. A program is initially written in pure C and compiled by the MAP C Compiler. Then, using feedback from the MAP C compiler, the program is successively transformed manually to achieve better performance. These transformations avoid certain inefficiencies, such as re-reading values from memory, loop slowdown caused by loop carried dependencies, and underutilizing memory bandwidth. We discuss the transformations in the context of the Wavelet Versatility Benchmark and the Gauss-Seidel iterative linear equation solver. FPGAs use a large number of pins to connect to memories. They do not have caches, but they have on-chip block RAM, allowing the programmer to decide what data stays on chip. Also, fine grain operation level parallelism combined with pipelining makes it possible for FPGAs to execute an inner loop body in one clock cycle. These characteristics provide a simple, deterministic performance model, allowing the programmer to work towards a well-defined goal: store hot data structures on chip either in block RAM or in registers, create inner loop bodies that execute in one clock cycle, and use the full memory bandwidth of the machine by loop unrolling.

The final report develops realistic benchmarks to assess the applicability of current memory massively parallel processors (MPPs) for real-time embedded applications, such as synthetic aperture radar (SAR) and space-time adaptive processing (STAP). A scalable real-time mapping of a generic two-dimensional processing chain applicable to SAR and STAP is developed and analyzed.

These briefing charts were presented at the Proceedings of the Eighth Annual High Performance Embedded Computing (HPEC) Workshop sponsored by DARPA Information Processing Technology Office. Some of the topics presented concerned computer systems, computational performance, DoD software, the development of cognitive computing systems,

Pre and Post Doppler Space-Time Adaptive Processing (STAP) architectures were considered for target implementations based on embedded High Performance Scalable Computing (HPSC) architectures leveraging commercially available processing technology from Analog Devices Super Harvard Architecture (SHARC) Digital Signal Processor (DSP). Algorithm partitioning and mapping was performed that demonstrated initial feasibility and then a sizing study was performed for a theoretical implementation. Further modeling and simulation studies utilized a discrete event simulator to perform detailed timing analysis and three different mappings of the Recursive Modified Gram Schmidt with Error Feedback (RMGSEF) algorithm in order to obtain insight into processor communication utilization and data latency. This effort culminated in a real time Radar demonstration of the RMGSEF algorithm that was implemented using parallel SHARC processors based on the High Performance Scalable Computer (HPSC) to perform the QR Decomposition (QRD). The demonstration Radar System incorporated 18 antenna elements over three pulse repetition intervals resulting in 34 degrees of freedom with performance of less than 15 ms of latency and a 42KHz sample rate. Further studies concentrated on alternative STAP solutions based on evolving Motorola PowerPC's and Field Programmable Gate Arrays (FPGAs).

The focus of this workshop is on high performance embedded computing technologies. The HPEC workshop will give U.S. Government funded researchers from academia, industry, and government, working in this important area, an opportunity to discuss techniques, approaches, and ongoing developments with relevance to real-time embedded military and signal processors. During this sixth year, the HPEC 2002 Workshop will have as its theme novel and emerging architectures for embedded computing. HPEC 2002 continues to provide a forum to present and discuss ongoing advances in these areas, and to gain an understanding of the status and future trends in embedded systems.

The Vector Signal and Image Processing Library (VSIPL) is an industry standard Application Programming Interface for embedded signal processing tasks. The High Performance Embedded Computing Software Initiative (HPEC-SI) program is a collaborative program to establish extensions to the VSIPL specification to support Object Oriented elements of the C++ programming language, and encapsulated support for data parallel processing. The program goals include the simultaneous threefold improvement in software portability, threefold improvement in developer productivity, and fifty percent improvement in software performance compared to standard practices. This report describes the efforts of the Georgia Tech Research Institute in support of the HPEC-SI program during the period from June 2006 through December 2007. These efforts included development of organizational strategies, participation in the HPEC-SI Applied Research and Development Working Groups, dissemination of program results to outside organizations via internet tools, and maintenance of a parallel computing software testbed for program participants, and development of an automated process for the configuration of certain types of computing nodes.

Up to now, the definition of space science missions was bounded by electronic components authorised by Space Agencies, i.e. developed on radiation tolerant technologies. Unfortunately, the microprocessors today available on such technologies have the computing throughput which was available about 10 years ago on the commercial market. Today, one of the main weakness of commercial components for space usage is their sensitivity to upsets, which generate transient faults during execution of flight software. Thus, to the condition to have light fault-tolerant architectures, the space community could define a new class of space science missions having very ambitious scientific goals and disrupting with classical missions thanks to high-performance embedded computers based on commercial electronic components.

The High Performance Embedded Computing Software Initiative is addressing the military's need to advance the state of embedded software development tools, libraries, and methodologies to retain the nation's military technology advantage in increasingly software-based systems. Key accomplishments include the completion of the first demonstration and the development of the Parallel VSIPL++ standard. Currently, the HPEC-SI effort is on track towards its goal of changing the state-of-the-practice in programming DoD HPEC SIP systems. This paper gives a brief overview of the HPEC-SI program objectives, technical objectives and program plans. The HPEC-SI program is organized around demonstrations, standards development, and applied research. Each of these activities is overseen by a Working Group. The demonstrations team Prime contractors with FFRDC or academic partners to use currently defined standards, evaluate their performance, and report on how well their needs are being met. The first demonstration was with the Common Imagery Processor (CIP) and successfully showed the use of MPI communication standard and the VSIPL computation standard to achieve portability (while preserving performance) across shared servers and distributed memory embedded systems. The Development Working Group is extending the VSIPL standard to include parallel object-oriented software practices already prototyped by the research community. This effort is tightly coupled with military demonstrations; it provides the next generation of standards with direct feedback from the military user base. The Applied Research Working Group is also taking a longer term view to assess the potential impact of a variety of emerging technologies, such as fault tolerance and dynamic scheduling, self-optimization, and next generation, high productivity languages. Thirty-one briefing charts summarize the presentation.

The Embedded Computing activities supported under this contract have been in support of multiple DARPA programs and efforts in support of the development and application of embedded computing. These activities have included: the Embeddable High Performance Computing (EHPC) Program, the Adaptive Computing Systems (ACS) Program, the Just In Time Hardware (JITH) efforts, the Data Intensive Systems (DIS) Program, the Mobile Autonomous Robotic Systems (MARS) Program, the Software for Distributed Robots (SDR) Program, the Quorum Program, the Next Generation Internet (NGI) Program/Advanced High Speed Communications, the Power Aware Computing and Communications (PAC/C) Program, the Model-Based Integration of Embedded Software (MoBIES) Program, the Software Enabled Control (SEC) Program, the Digital Radio Frequency Tags (DRaFT) Program, the Polymorphous Computing Architectures (PCA) Program, the Mission Specific Processing (MSP) Program, the High Productivity Computing Systems (HPCS) Program, the Clockless Logic Analysis, Systems, and Synthesis (CLASS) Program, the Architectures for Cognitive Information Processing (ACIP) Program, Graphics Processing Unit (GPU) for Computer Generated Forces (CGF) Program, and Joint Battle Command activities; developing activities including study (initial potential program investigation activities) efforts such as the electronic Textiles (e-Textiles) effort; the assessment and development of new program concepts; and the investigation of new embedded processing, computing architectures, communications, system development support, and software technologies. This set of programs and related technical activities address novel and advanced processing technologies that enable new and expanded performance and operational capabilities for high value embedded and high performance computing applications.

The availability of many-core computing platforms enables a wide variety of technical solutions for systems across the embedded, high-performance and cloud computing domains. However, large scale manycore systems are notoriously hard to optimise. Choices regarding resource allocation alone can account for wide variability in timeliness and energy dissipation (up to several orders of magnitude). Dynamic Resource Allocation in Embedded, High-Performance and Cloud Computing covers dynamic resource allocation heuristics for manycore systems, aiming to provide appropriate guarantees on performance and energy efficiency. It addresses different types of systems, aiming to harmonise the approaches to dynamic allocation across the complete spectrum between systems with little flexibility and strict real-time guarantees all the way to highly dynamic systems with soft performance requirements. Technical topics presented in the book include: • Load and Resource Models• Admission Control• Feedback-based Allocation and Optimisation• Search-based Allocation Heuristics• Distributed Allocation based on Swarm Intelligence• Value-Based AllocationEach of the topics is illustrated with examples based on realistic computational platforms such as Network-on-Chip manycore processors, grids and private cloud environments.

Embedded systems often must adhere to strict sire, weight, and power (SWAP) constraints and yet provide tremendous computational throughput. Increasing the difficulty of this challenge, there is a trend to utilize commercial-of-the-shelf (COTS) components in the design of such systems to reduce both total cost and time to market. Two embedded high performance radar applications are investigated in this effort: synthetic aperture radar (SAR) and space-time adaptive processing (STAP). Advanced techniques for optimally configuring and utilizing the components of a commercially particular multicomputer platform are described for these two applications. Although a particular platform is target in this study - Mercury Computer Systems' RACE multicomputer - the techniques described in this report are generic and could be applied to a range of different computational platforms. For the SAR application, a system performance model in the context of SWAP, is developed based on mathematical programming. An optimization technique using a combination of constrained nonlinear and integer programming is developed to determine system configurations that minimize SWAP. A major challenge of implementing parallel STAP algorithms on multiprocessor systems is determining the best method for distributing the 3-D data cube across processors of the multiprocessor system and scheduling communication within each phase of computation.

This briefing describes an effort to implement advanced Shipboard Ballistic Missile Defense (SBMD) application algorithms utilizing HPEC-SI. Shipboard application code, previously written in the C programming language for conventional COTS PowerPC-based embedded architectures, is being converted by Lockheed Martin MS2, as an HPEC-SI Demonstration, to run under the HPEC-SI API. The C code, designed to run in a C environment, will be converted to the HPEC-SI API standard to run under a true C++ Object Oriented environment, and will eventually take advantage of the HPEC-SI parallel processing features. Of particular interest in this conversion is a comparison of key DoD processing algorithms executed on a conventional, embedded processing architecture using C and C application libraries, as compared with execution in an embedded HPEC-SI processing environment. In this briefing, we describe the porting of several of the signal processing algorithms that have been developed using C-based VSIPL, and port them to the HPEC-SI VSIPL++ API under development. As part of this process, the HPEC-SI community will receive valuable feedback regarding the HPEC-SI API implementation, including the development process, development metrics, development environment issues and key library functions. Eventually, the open architecture HPEC-SI VSIPL++ code developed for the Navy and MDA will be ported to a tactical system for deployment on Aegis cruisers and destroyers.

The final report frames the communication scheduling problems associated with realistic real-time embedded applications on scalable massively parallel processors. These applications require high sustained processing rates, high sustained message passing rates, real-time services at the processing modes, and the most significant risk area of real-time internode communication services.

Over the last decade, the performance capabilities of FPGAs have increased exponentially. Leading vendors such as Xilinx and Altera have improved the functionality of their reconfigurable devices through the inclusion of memory, processors, multi-gigabit transceivers, and multipliers to the basic FPGA architecture. The result is a flexible, high performance processing device able to perform low latency, parallel processing tasks with low power consumption. In order to exploit the obvious benefits of FPGA technology in embedded systems, Nallatech has developed a range of FPGA-centric COTS products based upon the company's modular DIME-II architecture capable of TeraOPS performance. Customers using Nallatech products such as the BenNUEY-PC104+ are able to harness the full capability of advanced Virtex-II and Virtex-II Pro Xilinx FPGAs. With a range of motherboard form factors including PC104plus, VME, PCI and cPCI and a catalogue of plug and play DIME-II modules, embedded system developers can quickly build a flexible, high performance processing system tailored to the requirements of a specific application.

Challenges by Domain * Air: Persistent air dominance is at risk * Increasingly effective air defenses * Proliferation of 5th generation fighters, cheap cruise missiles, and UASs * Light-speed war possibilities are terrifying * Space: Now a contested domain * Increasingly important * Increasingly vulnerable * Cyber: Cyber warfare has begun * We don't control the battlespace * We rely on it more and more * We can't find the enemy.

This application of scalable high performance computing to real time embedded systems is expanding. Traditional benchmarks and notions of scalability drawn from the scientific parallel computing community are of limited relevance when timing requirements must be met within strict size, weight, and power requirements. This paper proposes a bench marking methodology for real time embedded applications, including a relevant notion of scalability. The essential point is to give equal emphasis to timing and functional specifications. We use a test bench on the machine itself to realistically impulse the function or system under test. Metrics that measure the steady state performance account for limitations of non real time system software. The key metric is the minimum processor size required to meet the real time specifications for a given problem size. The scalability of the embedded processor can then be characterized in terms of the rate of increase of this minimum machine size as the problem (and potentially the real time requirement) is scaled.