Downloads & Free Reading Options - Results

The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into modern high-performance computing (HPC) systems. We examine how QPUs can be integrated into current and future HPC system architectures by accounting for functional and physical design requirements. We identify two integration pathways that are differentiated by infrastructure constraints on the QPU and the use cases expected for the HPC system. This includes a tight integration that assumes infrastructure bottlenecks can be overcome as well as a loose integration that assumes they cannot. We find that the performance of both approaches is likely to depend on the quantum interconnect that serves to entangle multiple QPUs. We also identify several challenges in assessing QPU performance for HPC, and we consider new metrics that capture the interplay between system architecture and the quantum parallelism underlying computational performance.

The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into modern high-performance computing (HPC) systems. We examine how QPUs can be integrated into current and future HPC system architectures by accounting for functional and physical design requirements. We identify two integration pathways that are differentiated by infrastructure constraints on the QPU and the use cases expected for the HPC system. This includes a tight integration that assumes infrastructure bottlenecks can be overcome as well as a loose integration that assumes they cannot. We find that the performance of both approaches is likely to depend on the quantum interconnect that serves to entangle multiple QPUs. We also identify several challenges in assessing QPU performance for HPC, and we consider new metrics that capture the interplay between system architecture and the quantum parallelism underlying computational performance.

The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into modern high-performance computing (HPC) systems. We examine how QPUs can be integrated into current and future HPC system architectures by accounting for functional and physical design requirements. We identify two integration pathways that are differentiated by infrastructure constraints on the QPU and the use cases expected for the HPC system. This includes a tight integration that assumes infrastructure bottlenecks can be overcome as well as a loose integration that assumes they cannot. We find that the performance of both approaches is likely to depend on the quantum interconnect that serves to entangle multiple QPUs. We also identify several challenges in assessing QPU performance for HPC, and we consider new metrics that capture the interplay between system architecture and the quantum parallelism underlying computational performance.

The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into modern high-performance computing (HPC) systems. We examine how QPUs can be integrated into current and future HPC system architectures by accounting for functional and physical design requirements. We identify two integration pathways that are differentiated by infrastructure constraints on the QPU and the use cases expected for the HPC system. This includes a tight integration that assumes infrastructure bottlenecks can be overcome as well as a loose integration that assumes they cannot. We find that the performance of both approaches is likely to depend on the quantum interconnect that serves to entangle multiple QPUs. We also identify several challenges in assessing QPU performance for HPC, and we consider new metrics that capture the interplay between system architecture and the quantum parallelism underlying computational performance.

The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into modern high-performance computing (HPC) systems. We examine how QPUs can be integrated into current and future HPC system architectures by accounting for functional and physical design requirements. We identify two integration pathways that are differentiated by infrastructure constraints on the QPU and the use cases expected for the HPC system. This includes a tight integration that assumes infrastructure bottlenecks can be overcome as well as a loose integration that assumes they cannot. We find that the performance of both approaches is likely to depend on the quantum interconnect that serves to entangle multiple QPUs. We also identify several challenges in assessing QPU performance for HPC, and we consider new metrics that capture the interplay between system architecture and the quantum parallelism underlying computational performance.

Energy minimization of Ising spin-glasses has played a central role in statistical and solid-state physics, facilitating studies of phase transitions and magnetism. Recent proposals suggest using Ising spin-glasses for non-traditional computing as a way to harness the nature's ability to find min-energy configurations, and to take advantage of quantum tunneling to boost combinatorial optimization. Laboratory demonstrations have been unconvincing so far and lack a non-quantum baseline for definitive comparisons. In this work we (i) design and evaluate new computational techniques to simulate natural energy minimization in spin glasses and (ii) explore their application to study design alternatives in quantum adiabatic computers. Unlike previous work, our algorithms are not limited to planar Ising topologies. In one CPU-day, our branch-and-bound algorithm finds ground states on 100 spins, while our local search approximates ground states on 1, 000, 000 spins. We use this computational tool as a simulator to study the significance of hyper-couplings in the context of recently implemented adiabatic quantum computers.

Todd Gamblin, a computer scientist at Lawrence Livermore National Laboratory, joined us to talk about Moore's Law, his work at Lawrence Livermore National Laboratory, the components of a micro-chip, and High Performance Computing.

Government Publishing Office U.S. Congress House of Representatives Committee on Science H.R. 4218, HIGH-PERFORMANCE COMPUTING REVITALIZATION ACT OF 2004 Date(s) Held: 2004-05-13 108th Congress, 2nd Session GPO Document Source: CHRG-108hhrg93214 Superintendents of Documents ID: Y 4.SCI 2 Witnesses: Dr. John H. Marburger, III, Director, White House Office of Science and Technology Policy Dr. Irving Wladawsky-Berger, Vice President for Technology and Strategy, IBM Corporation Dr. Rick Stevens, Director, Mathematics and Computer Science Division, Argonne National Laboratory Dr. Daniel A. Reed, William R. Kenan, Jr. Eminent Professor, University of North Carolina at Chapel Hill Related Items: United States House Bill 4107 (108th Congress) United States House Bill 4218 (108th Congress) United States House Bill 4218 (108th Congress) Public Law 102-194 Public Law 105-305 Congressional Serial No. 108-55

This issue of HPC Insights showcases recent work on high-fidelity simulations of jet atomization and first principles modeling of modern jet-engine combustors; demonstrates how HPCMP CREATE tools continue to impact DoD acquisition programs; and with an eye toward the future, highlights some of our HPC Internship Program (HIP) project results. We also announce DREN network upgrades as well as the installation of new HPC machines at the DSRCs in ERDC and ARL as part of the 2016 Technology Insertion (TI) and the requirements gathering for TI-17.

Includes bibliographical references and index

Score-P is a measurement infrastructure originally designed for the analysis and optimization of the performance of HPC codes. Recent extensions of Score-P and its associated tools now also allow the investigation of energy-related properties and support the user in the implementation of corresponding improvements. Since it would be counterproductive to completely ignore performance issues in this connection, the focus should not be laid exclusively on energy. We therefore aim to optimize software with respect to an objective function that takes into account energy and run time.

This grant was used for upgrading an SGI Power Challenge L supercomputer and for the acquisition of 3 SGI O2 workstations to serve DoD research projects in three general areas: (1) Research on the p- and hp-versions of the Finite Element Method conducted by the Center for Computational Mechanics. (2) Research on non-linear control systems conducted in the Department of Systems Science and Mathematics. (3) Rotorcraft analysis and simulation conducted in the Department of Mechanical Engineering.

High Performance Computing (HPC) is a key, enabling technology that is essential to assure that U.S. Forces maintain dominance on the battlefield with minimal risk to life, even against numerically superior forces. Tracing requirements from the President's National Security Strategy to our National Military Strategy as defined by the Military Services, Joint Chiefs of Staff, and the warfighting Commanders in Chief (ClNCs), one common denominator prevails-the need for militarily superior technology. Technology is a key discriminator in our deterrence of conflicts; failing to deter aggression, technology can be the difference between success and failure on the battlefield. HPC enables advanced modeling and simulation concepts and capabilities that can be used to assess the value of individual components or new weapon systems' projected performance levels. Data collected from modeling and simulation will assist milestone decisions by pointing to research, development, test and evaluation (RDT&E) of most value to the warfighter. Through the use of HPC resources for example, it is possible to simulate the capabilities of a new weapon system and to measure that system's impact on existing tactics and the predicted outcome of a military engagement (using tens of thousands of entity types). As a result, senior DoD leadership will have data to assist in the decision-making process as early as possible. These data will provide information about whether to proceed, modify, or cancel a program and where to best invest our RDT&E resources. Other mission-critical areas that could be greatly improved by advanced modeling and simulations using HPC include ocean modeling and weather prediction, bomb damage assessment, water tampering determinations, modeling of radio frequency systems and antenna designs, environmental impacts/ cleanup, and counter-proliferation and counter-terrorism scenarios.

A number of improvements to PDEPACK have been made. These include the development of parallel discretization methodologies and sparse/iterative PDE solvers. (AN)

This research project investigated techniques to develop a High Performance Computing (HPC) grid infrastructure to operate as an interactive research and development tool. Current HPC grid architectures are designed for batch applications, where users submit their job requests, and then wait for notification of job completion. In the batch environment, the user lacks direct control over the execution of their application. To meet this need for accessing and processing data interactively in near real-time, the Air Force Research Laboratory/ Information Directorate developed an environment that stresses 'near real-time' user interaction with the application. This involved evaluating the various developing protocols for interactive grid computing, using the Globus Toolkit, and then selecting the one with the most growth potential. The grid architecture was evaluated by assembling and demonstrating an in-house interactive demonstration grid using in-house cluster assets and existing code, to verify proper operation on a small scale.

This book is a compilation of reports on all the work accomplished by NRL scientists and engineers and their collaborators using the DoD High Performance Computing Modernization Program's (HPCMP) resources for fiscal year 2006. The reports encompass work performed by researchers at all three NRL sites: Washington, DC; Stennis Space Center, Mississippi; and Monterey, California. These reports are categorized according to the primary Computational Technology Area (CTA) as specified by the HPCMP, and include resources at the Major Shared Resources Centers as well as the Distributed Centers. This volume includes three indexes for ease of reference. These are an author index, a site index, and an NRL hierarchical index of reports from the Branches and Divisions in the Laboratory.

For more than a decade, the HPCMP has supported a workforce that routinely uses HPC resources to solve many of the Department's most challenging scientific and engineering problems. This, in turn, helps the United States ensure military advantage and warfighting superiority on the 21st century battlefield. The Program enables scientists and engineers to further the Department's objectives through research, development, test, and evaluation (RDT&E) activities that support science and technology (S&T), and test and evaluation (T&E). These efforts focus on the most complex, and highest priority defense challenges. This annual report highlights a small portion of the work performed to support the Department. The HPCMP achieves the Program's mission and vision by focusing on five specific goals. Each activity within the program supports one or more of these goals, with progress tracked and successes delineated. These five goals are: 1) acquire, deploy, operate, and maintain best-value supercomputers; 2) acquire, develop, deploy, and support software applications and computational work environments that enable critical DoD research, development, and test challenges to be analyzed and solved; 3) acquire, deploy, operate and maintain a communications network that enables effective access to supercomputers and to distributed S&T/T&E computing environments; 4) promote collaborative relationships among the DoD computational science community, the national computational science community, and minority serving institutions; and 5) continuously educate the research, development, test, and evaluation workforce with the knowledge needed to employ computational modeling effectively and efficiently.

It is important to put stress on a current and innovative teaching and thus leading subjects for students nowadays. This is valid for universities primary. An example of conducting the subject „HPC and Grid Architecture“ in the environment MOODLE is introduced in the article. After making research among students who had passed this subject and after making comparison with other possibilities that are available online, the output was made. Issues discussed are focused on its interesting thing, the way of lecture and availability of subject´s content.

It is important to put stress on a current and innovative teaching and thus leading subjects for students nowadays. This is valid for universities primary. An example of conducting the subject „HPC and Grid Architecture“ in the environment MOODLE is introduced in the article. After making research among students who had passed this subject and after making comparison with other possibilities that are available online, the output was made. Issues discussed are focused on its interesting thing, the way of lecture and availability of subject´s content.

It is important to put stress on a current and innovative teaching and thus leading subjects for students nowadays. This is valid for universities primary. An example of conducting the subject „HPC and Grid Architecture“ in the environment MOODLE is introduced in the article. After making research among students who had passed this subject and after making comparison with other possibilities that are available online, the output was made. Issues discussed are focused on its interesting thing, the way of lecture and availability of subject´s content.

The final report develops realistic benchmarks to assess the applicability of current memory massively parallel processors (MPPs) for real-time embedded applications, such as synthetic aperture radar (SAR) and space-time adaptive processing (STAP). A scalable real-time mapping of a generic two-dimensional processing chain applicable to SAR and STAP is developed and analyzed.

Well-designed network traffic collection provides a wealth of information regarding what a network-centric system is doing. Analysis tools examine the data and readily help answer what, but why and how may not be attainable, even with advanced analytics. Collecting device status information can augment network traffic information to help answer why and how. To answer these questions, the Aberdeen Test Center developed an active device status collector and collaborated with the US Army Research Laboratory to develop a high-performance-computing solution for correlating device status data with network traffic data.

The primary objectives of the Phase II of the project are: (a) implement the context-aware parallel random number generator (CPRNG), developed in Phase I of this project, (b) implement the interstream correlation (ISC) test so that the quality of the random numbers (RNs) used by applications are evaluated and quality metrics are reported on demand. Both objectives have been accomplished. Beyond these objectives, additional design and implementation contributions have been accomplished. A flexible CPRNG-ISC Test (CIT) framework was developed and implemented so that a third party tester such as Dieharder or TestU01 can be run along with ISC test to corroborate or compare ISC test results with those from the well-known single-stream test batteries. The CPRNG Library facilitates implementation and use of other random number generators within the test framework easily.

The primary objectives of the Phase II of the project are: (a) implement the context-aware parallel random number generator (CPRNG), developed in Phase I of this project, (b) implement the interstream correlation (ISC) test so that the quality of the random numbers (RNs) used by applications are evaluated and quality metrics are reported on demand. Both objectives have been accomplished. Beyond these objectives, additional design and implementation contributions have been accomplished. A flexible CPRNG-ISC Test (CIT) framework was developed and implemented so that a third party tester such as Dieharder or TestU01 can be run along with ISC test to corroborate or compare ISC test results with those from the well-known single-stream test batteries. The CPRNG Library facilitates implementation and use of other random number generators within the test framework easily.

Trimester 1 - 2017/2018

This thesis focused on creating an object-oriented software architecture around which tools can be created to increase the usability of stochastic simulations such as IWARS and Pythagoras on high performance computing clusters. The objective of the architecture was to enable the user to design and execute simulation experiments using a platform-independent client and server to create a common interface for various simulations. The interface input is used to select the experimental factors of interest to the research analyst and then to create the scenario files for each simulation run with minimal human intervention. To develop the architecture the current state of the art was explored, a proposed process flow was developed. This process flow was then vetted by operations researchers from several organizations. A prototype application was developed based on the software architecture. The prototype revealed great benefit in this type of tool.

This thesis endeavors to determine how effective a role high performance computing played in the Program Definition and Risk Reduction (PDRR) and early Engineering and Manufacturing Development (EMD) phases of the RAH-66 Comanche program. In so doing, the various modeling and simulation efforts used in the Comanche program are explored and their utility and efficacy determined. This study provides insights into the places to insert high performance computing into the simulation based acquisition process for best effect. In addition, it uncovers the best uses of modeling and simulation in the Comanche program, which can serve as a guide for other simulation based acquisition programs.

This thesis endeavors to determine how effective a role high performance computing played in the Program Definition and Risk Reduction (PDRR) and early Engineering and Manufacturing Development (EMD) phases of the RAH-66 Comanche program. In so doing, the various modeling and simulation efforts used in the Comanche program are explored and their utility and efficacy determined. This study provides insights into the places to insert high performance computing into the simulation based acquisition process for best effect. In addition, it uncovers the best uses of modeling and simulation in the Comanche program, which can serve as a guide for other simulation based acquisition programs.

IRPF90 is a Fortran programming environment which helps the development of large Fortran codes. In Fortran programs, the programmer has to focus on the order of the instructions: before using a variable, the programmer has to be sure that it has already been computed in all possible situations. For large codes, it is common source of error. In IRPF90 most of the order of instructions is handled by the pre-processor, and an automatic mechanism guarantees that every entity is built before being used. This mechanism relies on the {needs/needed by} relations between the entities, which are built automatically. Codes written with IRPF90 execute often faster than Fortran programs, are faster to write and easier to maintain.

GPU4HOST’s GPU dedicated server offers unmatched computing power for researchers working on big data, simulations, and AI-driven innovation.

GPU4HOST’s GPU dedicated server offers unmatched computing power for researchers working on big data, simulations, and AI-driven innovation.

GPU4HOST’s GPU dedicated server offers unmatched computing power for researchers working on big data, simulations, and AI-driven innovation.

GPU4HOST’s GPU dedicated server offers unmatched computing power for researchers working on big data, simulations, and AI-driven innovation.

Knowing the future weather on the battlefield with high certainty can result in a higher advantage over the adversary. To create this advantage for the United States, the U.S. Navy utilizes the Coupled Ocean/Atmosphere Mesoscale Prediction System (COAMPS) to create high spatial resolution, regional, numerical weather prediction (NWP) forecasts. To compute a forecast, COAMPS runs on high performance computing (HPC) systems. These HPC systems are large, dedicated supercomputers with little ability to scale or move. This makes these systems vulnerable to outages without a costly, equally powerful secondary system. Recent advancements in cloud computing and virtualization technologies provide a method for high mobility and scalability without sacrificing performance. This research used standard benchmarks in order to quantitatively compare a virtual machine (VM) to a native HPC cluster. The benchmark tests showed that the VM was feasible platform for executing HPC applications. Then we ran the COAMPS NWP on a VM within a cloud infrastructure to prove the ability to run a HPC application in a virtualized environment. The VM COAMPS model run performed better than the native HPC machine model run. These results show that VM and cloud computing technologies can be used to run HPC applications for the Department of Defense

Knowing the future weather on the battlefield with high certainty can result in a higher advantage over the adversary. To create this advantage for the United States, the U.S. Navy utilizes the Coupled Ocean/Atmosphere Mesoscale Prediction System (COAMPS) to create high spatial resolution, regional, numerical weather prediction (NWP) forecasts. To compute a forecast, COAMPS runs on high performance computing (HPC) systems. These HPC systems are large, dedicated supercomputers with little ability to scale or move. This makes these systems vulnerable to outages without a costly, equally powerful secondary system. Recent advancements in cloud computing and virtualization technologies provide a method for high mobility and scalability without sacrificing performance. This research used standard benchmarks in order to quantitatively compare a virtual machine (VM) to a native HPC cluster. The benchmark tests showed that the VM was feasible platform for executing HPC applications. Then we ran the COAMPS NWP on a VM within a cloud infrastructure to prove the ability to run a HPC application in a virtualized environment. The VM COAMPS model run performed better than the native HPC machine model run. These results show that VM and cloud computing technologies can be used to run HPC applications for the Department of Defense

Knowing the future weather on the battlefield with high certainty can result in a higher advantage over the adversary. To create this advantage for the United States, the U.S. Navy utilizes the Coupled Ocean/Atmosphere Mesoscale Prediction System (COAMPS) to create high spatial resolution, regional, numerical weather prediction (NWP) forecasts. To compute a forecast, COAMPS runs on high performance computing (HPC) systems. These HPC systems are large, dedicated supercomputers with little ability to scale or move. This makes these systems vulnerable to outages without a costly, equally powerful secondary system. Recent advancements in cloud computing and virtualization technologies provide a method for high mobility and scalability without sacrificing performance. This research used standard benchmarks in order to quantitatively compare a virtual machine (VM) to a native HPC cluster. The benchmark tests showed that the VM was feasible platform for executing HPC applications. Then we ran the COAMPS NWP on a VM within a cloud infrastructure to prove the ability to run a HPC application in a virtualized environment. The VM COAMPS model run performed better than the native HPC machine model run. These results show that VM and cloud computing technologies can be used to run HPC applications for the Department of Defense

Knowing the future weather on the battlefield with high certainty can result in a higher advantage over the adversary. To create this advantage for the United States, the U.S. Navy utilizes the Coupled Ocean/Atmosphere Mesoscale Prediction System (COAMPS) to create high spatial resolution, regional, numerical weather prediction (NWP) forecasts. To compute a forecast, COAMPS runs on high performance computing (HPC) systems. These HPC systems are large, dedicated supercomputers with little ability to scale or move. This makes these systems vulnerable to outages without a costly, equally powerful secondary system. Recent advancements in cloud computing and virtualization technologies provide a method for high mobility and scalability without sacrificing performance. This research used standard benchmarks in order to quantitatively compare a virtual machine (VM) to a native HPC cluster. The benchmark tests showed that the VM was feasible platform for executing HPC applications. Then we ran the COAMPS NWP on a VM within a cloud infrastructure to prove the ability to run a HPC application in a virtualized environment. The VM COAMPS model run performed better than the native HPC machine model run. These results show that VM and cloud computing technologies can be used to run HPC applications for the Department of Defense

The panelists talk about high performance computing with Colin Cornaby.

The electromagnetic modeling of packages and interconnects plays a very important role in the design of high-speed digital circuits, and is most efficiently performed by using computer-aided design algorithms. In recent years, packaging has become a critical area in the design of high-speed communication systems and fast computers, and the importance of the software support for their development has increased accordingly. Throughout this project, our efforts have focused on the development of modeling and simulation techniques and algorithms that permit the fast computation of the electrical parameters of interconnects and the efficient simulation of their electrical performance.

Lectures from the National Programme on Technology Enhanced Learning - Computer Science and Engineering - High Performance Computing

The feasibility of probabilistic inference based anomaly detection was determined, and those results were applied to wide area surveillance. An abstract - level autonomous information processing framework was developed that provided continuous monitoring and real - time anomaly detection over hundreds of square kilometer areas. The anomaly recognition and detection (AnRAD) system was built as a cogent confabulation network. It represented road traffic using a set of features extracted from a Ground Moving Target Indicator (GMTI) input stream and performed likelihood-ratio testing on a set of key features to detect abnormal vehicle behavior. Due to its low learning and recall complexities, the AnRAD supported incremental learning, which was proved to enhance the detection accuracy. A self - structuring technique was developed that learned the structure of a probabilistic inference network from unlabeled data. Without any assumption of the distribution of data, mutual information between features was leveraged to learn a succinct network configuration. Compared to several existing anomaly detection methods, the proposed approach provided higher detection performances and excellent reasoning capabilities. Massive parallelism was inherent to the inference model and accelerated the detection process using state- of-the-art multicore processors including graphic processor units (GPUs) and Intel Xeon Phi processors. Experimental results showed significant speedups, which can enable real-time applications with high-volume data streams.

As advancements in CMOS technology trend toward ever increasing core counts in chip multiprocessors for high-performance embedded computing, the discrepancy between on- and off-chip communication bandwidth continues to widen due to the power and spatial constraints of electronic off-chip signalling. Silicon photonics-based communication offers many advantages over electronics for network-on-chip design, namely power consumption that is effectively agnostic to distance traveled at the chip- and board-scale, even across chip boundaries. In this work we develop a design for a photonic network-on-chip with integrated DRAM I/O interfaces and compare its performance to similar electronic solutions using a network-on-chip simulation environment that uniquely captures the physical characteristics of the photonic layer. When used in a circuit-switched network, silicon nanophotonic switches offer higher bandwidth density, low power transmission, and relaxed physical constraints such as pin count and board layout. These effects add up to over 10x better performance and 20-3Ox lower power for projective transform, matrix multiply, and Fast Fourier Transform (FFT), all key algorithms in embedded real-time signal and image processing.

This investigation of High Performance Computing (HPC) Multicast for High-Speed Publication-Subscription (Pub-Sub) sought to deliver both insight into and implementation of high-performance multicast solutions that enable better utilization of cloud resources. These solutions combine improved scalability with increased consistency ensuring that expected and necessary system conditions are thus met for a myriad of critical national-asset applications that are likely to move to the cloud in the next decade. In the context of this effort, the applicability of the oft-invoked Consistency, Availability and Partition tolerance (CAP) theorem was explored within specific environments of commonly deployed clouds, and novel insights into CAP's tradeoffs were developed between CAP and its conclusion that a replicated service can possess just two of the three. It was determined that there are replicated services for which the applicability of CAP is unclear specifically, the scalable soft-state services that run in the first-tier of a single cloud-computing data center. The challenge is that such services live in a single data center and run on redundant networks. Partitioning events involve single machines or small groups, and are treated as node failures; thus, the CAP proof doesn't apply in a formal sense, as it s proven by forcing a replicated service to respond to conflicting requests during a partitioning failure, triggering inconsistency. Nonetheless, most developers believe in a generalized CAP folk theorem, holding that scalability and elasticity are incompatible with strong forms of consistency. We designed, implemented, and benchmarked the Isis2 platform: a first-tier consistency alternative that replicates data, combines agreement on update ordering with amnesia freedom, and supports both good scalability and fast response. A team of students was lead in the application of Isis2 to build a large-scale distributed computer-vision landmark-recognition system,

The goal of this effort was to stimulate and facilitate wider usage of high performance computing (HPC) across the private sector to propel productivity, innovation, and competitiveness. The council on Competitiveness (Council) confirmed 14 industrial / 1 Museum executives to give presentations at SC07, the annual international supercomputing conference to be held November 12-16, 2007. Presentations focused on how their organizations are using high performance computing to drive competitive advantage. The Council targeted four Masterworks speakers representing Ping Golf, Whirlpool, Goodyear, and Pioneer Hi-Bred to conduct case studies on the business and competitiveness value they have received from using HPC. Case studies explain in laymen's terms the problems these firms solved and the returns they achieved are necessary and important tools for building the business case for HPC and expanding its use across the U.S. industrial base, particularly among small and mid-sized companies that are in DoD's supply chain but have not yet embraced this technology.

This report of a hearing begins with an opening statement by Senator J. Bennett Johnston, Chairman of the Committee, and prepared statements from Committee members Larry E. Craig and Pete V. Domenici. The text of the bill, which provides for continued U.S. leadership in high-performance computing, is then presented, followed by additional statements from Senators Wendell H. Ford, Albert Gore, Jr., Jeff Bingaman, and Malcolm Wallop Testimony is also included from Siegfried S. Hecker, Director of the Los Alamos National Laboratory; Kenneth M. King, president of EDUCOM; David B. Nelson, Executive Director of the Office of Energy Research, Department of Energy; Glenn Ricart, president of FARNET; Lloyd M. Thorndyke, chief executive officer of DataMax, Inc.; and Eugene Wong, Associate Director of Physical Sciences and Engineering, Office of Science and Technology, Executive Office of the President. Responses to additional questions and additional materials submitted for the record are also provided. (DB)

Rapid increases in the complexity of algorithms for real-time signal processing applications have led to performance requirements exceeding the capabilities of conventional digital signal processor (DSP) architectures. Many applications, such as autonomous sonar arrays, are distributed in nature and amenable to parallel computing on embedded systems constructed from multiple DSPs networked together. However, to realize the full potential of such applications, a lightweight service for message-passing communication and parallel process coordination is needed that is able to provide high throughput and low latency while minimizing processor and memory utilization. This paper presents the design and analysis of such a service, based on the Message Passing Interface (MPI) specification, for unicast and collective communications.