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Embedded systems are often subject to real-time constraints. Such systems require determinism to ensure that task deadlines are met. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines. Knowledge of bounds on worst-case execution times (WCET) of tasks is a critical piece of information required by schedulability analysis. Static timing analysis derives these bounds on WCETs, but requires that bounds on loop iterations be known statically, i.e., at compile time. This often limits the class of applications that may be analyzed by static timing analysis and, hence, used in a real-time system. Another limiting factor for real-time system design is the class of processors that may be used. Typically, modern, complex, processors may not be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks. The main reason is that these features introduce non-determinism to task execution, which can only be resolved at run-time. The contributions of this work are two-fold. First, we show how the constraint concerning statically bound loops may be relaxed and applied to make dynamic decisions at run-time to obtain power savings. Second, we introduce a new paradigm, which proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors. To the best of our knowledge, these methods of (a) using run-time information to obtain accurate upper bounds for loops and using that information to achieve energy savings, and (b) hardware/software interactions to calculate WCET results for out-of-order processors, are the first of their kind. ©2008 Microsoft Corporation. All rights reserved.

Embedded systems are often subject to real-time constraints. Such systems require determinism to ensure that task deadlines are met. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines. Knowledge of bounds on worst-case execution times (WCET) of tasks is a critical piece of information required by schedulability analysis. Static timing analysis derives these bounds on WCETs, but requires that bounds on loop iterations be known statically, i.e., at compile time. This often limits the class of applications that may be analyzed by static timing analysis and, hence, used in a real-time system. Another limiting factor for real-time system design is the class of processors that may be used. Typically, modern, complex, processors may not be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks. The main reason is that these features introduce non-determinism to task execution, which can only be resolved at run-time. The contributions of this work are two-fold. First, we show how the constraint concerning statically bound loops may be relaxed and applied to make dynamic decisions at run-time to obtain power savings. Second, we introduce a new paradigm, which proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors. To the best of our knowledge, these methods of (a) using run-time information to obtain accurate upper bounds for loops and using that information to achieve energy savings, and (b) hardware/software interactions to calculate WCET results for out-of-order processors, are the first of their kind. ©2008 Microsoft Corporation. All rights reserved.

Embedded systems are often subject to real-time constraints. Such systems require determinism to ensure that task deadlines are met. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines. Knowledge of bounds on worst-case execution times (WCET) of tasks is a critical piece of information required by schedulability analysis. Static timing analysis derives these bounds on WCETs, but requires that bounds on loop iterations be known statically, i.e., at compile time. This often limits the class of applications that may be analyzed by static timing analysis and, hence, used in a real-time system. Another limiting factor for real-time system design is the class of processors that may be used. Typically, modern, complex, processors may not be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks. The main reason is that these features introduce non-determinism to task execution, which can only be resolved at run-time. The contributions of this work are two-fold. First, we show how the constraint concerning statically bound loops may be relaxed and applied to make dynamic decisions at run-time to obtain power savings. Second, we introduce a new paradigm, which proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors. To the best of our knowledge, these methods of (a) using run-time information to obtain accurate upper bounds for loops and using that information to achieve energy savings, and (b) hardware/software interactions to calculate WCET results for out-of-order processors, are the first of their kind. ©2008 Microsoft Corporation. All rights reserved.

The embedded systems running real-time applications, for which Ada was designed, require their own mechanisms for the management of dynamically allocated storage. There is a need for packages which manage their own internalo structures to control their deallocation as well, due to the performance implications of garbage collection by the KAPSE. This places a requirement upon the design of generic packages which manage generically structured private types built-up from application-defined input types. These kinds of generic packages should figure greatly in the development of lower-level software such as operating systems, schedulers, controllers, and device driver; and will manage structures such as queues, stacks, link-lists, files, and binary multary (hierarchical) trees. Controlled to prevent inadvertent de-designation of dynamic elements, which is implicit in the assignment operation A study was made of the use of limited private type, in solving the problems of controlling the accumulation of anonymous, detached objects in running systems. The use of deallocator prodecures for run-down of application-defined input types during deallocation operations during satellites.

The National Aeronautics and Space Administration, United Technologies Research Center and Virginia Polytechnic and State University have contracted to pursue multi-disciplinary research into boundary layer ingesting (BLI) propulsors for generation after next environmentally responsible subsonic fixed wing aircraft. This Robust Design for Embedded Engine Systems project first conducted a high-level vehicle system study based on a large commercial transport class hybrid wing body aircraft, which determined that a 3 to 5 percent reduction in fuel burn could be achieved over a 7,500 nanometer mission. Both pylon-mounted baseline and BLI propulsion systems were based on a low-pressure-ratio fan (1.35) in an ultra-high-bypass ratio engine (16), consistent with the next generation of advanced commercial turbofans. An optimized, coupled BLI inlet and fan system was subsequently designed to achieve performance targets identified in the system study. The resulting system possesses an inlet with total pressure losses less than 0.5%, and a fan stage with an efficiency debit of less than 1.5 percent relative to the pylon-mounted, clean-inflow baseline. The subject research project has identified tools and methodologies necessary for the design of next-generation, highly-airframe-integrated propulsion systems. These tools will be validated in future large-scale testing of the BLI inlet / fan system in NASA's 8 foot x 6 foot transonic wind tunnel. In addition, fan unsteady response to screen-generated total pressure distortion is being characterized experimentally in a JT15D engine test rig. These data will document engine sensitivities to distortion magnitude and spatial distribution, providing early insight into key physical processes that will control BLI propulsor design.

One of the characteristics of real-time systems is concurrency. Designers of real-time systems have traditionally determined system concurrency at implementation time using the facilities of a cyclic executive. With the advent of programming language constructs for specifying concurrency, determining concurrency at design time has become a possibility. Several design methods, all of which are extensions of either Structured Design or Jackson System Development, provide heuristics to help the designer make concurrency decisions. The object-oriented approach, however, has no corresponding heuristics to aid designers of real-time systems. The purpose of this thesis was to develop heuristics to help designers make concurrency decisions in developing object-oriented designs of real-time systems. This was accomplished by examining existing heuristics from other design methods and applying them to the object- oriented paradigm. Four heuristics were developed, the first of which exploits the potential in object-oriented design to model the problem-space. The other three heuristics deal with concurrency which is not necessarily reflected in the problem-space, but must be implemented for practical reasons. The heuristics were validated by applying them to a sample problem, then having the heuristics and the design of the sample problem evaluated by a group of software engineering experts.

One of the characteristics of real-time systems is concurrency. Designers of real-time systems have traditionally determined system concurrency at implementation time using the facilities of a cyclic executive. With the advent of programming language constructs for specifying concurrency, determining concurrency at design time has become a possibility. Several design methods, all of which are extensions of either Structured Design or Jackson System Development, provide heuristics to help the designer make concurrency decisions. The object-oriented approach, however, has no corresponding heuristics to aid designers of real-time systems. The purpose of this thesis was to develop heuristics to help designers make concurrency decisions in developing object-oriented designs of real-time systems. This was accomplished by examining existing heuristics from other design methods and applying them to the object- oriented paradigm. Four heuristics were developed, the first of which exploits the potential in object-oriented design to model the problem-space. The other three heuristics deal with concurrency which is not necessarily reflected in the problem-space, but must be implemented for practical reasons. The heuristics were validated by applying them to a sample problem, then having the heuristics and the design of the sample problem evaluated by a group of software engineering experts.

One of the characteristics of real-time systems is concurrency. Designers of real-time systems have traditionally determined system concurrency at implementation time using the facilities of a cyclic executive. With the advent of programming language constructs for specifying concurrency, determining concurrency at design time has become a possibility. Several design methods, all of which are extensions of either Structured Design or Jackson System Development, provide heuristics to help the designer make concurrency decisions. The object-oriented approach, however, has no corresponding heuristics to aid designers of real-time systems. The purpose of this thesis was to develop heuristics to help designers make concurrency decisions in developing object-oriented designs of real-time systems. This was accomplished by examining existing heuristics from other design methods and applying them to the object- oriented paradigm. Four heuristics were developed, the first of which exploits the potential in object-oriented design to model the problem-space. The other three heuristics deal with concurrency which is not necessarily reflected in the problem-space, but must be implemented for practical reasons. The heuristics were validated by applying them to a sample problem, then having the heuristics and the design of the sample problem evaluated by a group of software engineering experts.

This paper describes a generic approach to mitigate risk when reengineering for high throughput massively parallel systems. The approach entails baselining the existing system, capturing the functional requirements, estimating initial processing requirements through a high level analysis, benchmarking a subset of the functionality on a low throughput computer, and modeling the high throughput application to determine the detailed processing requirements for scaling.

This paper describes a generic approach to mitigate risk when reengineering for high throughput massively parallel systems. The approach entails baselining the existing system, capturing the functional requirements, estimating initial processing requirements through a high level analysis, benchmarking a subset of the functionality on a low throughput computer, and modeling the high throughput application to determine the detailed processing requirements for scaling.

In this paper we focus on some aspects related to modeling and formal verification of embedded systems. Many models have been proposed to represent embedded systems. These models encompass a broad range of styles, characteristics, and application domains and include the extensions of finite state machines, data flow graphs, communication processes and Petri nets. In this report, we have used a PRES+ model (Petri net based Representation for Embedded Systems) as an extension of classical Petri net model that captures concurrency, timing behaviour of embedded systems; it allows systems to be representative in different levels of abstraction and improves expressiveness by allowing the token to carry information. Modeling using PRES+, as discussed above, may be convenient for specifying the input behaviour because it supports concurrency. However, there is no equivalence checking method reported in the literature for PRES+ models to the best of our knowledge. In contrast, equivalence checking of FSMD models exist. As a first step, therefore, we seek to devise an algorithm to translate PRES+ models to FSMD models and we seek to hand execute our algorithm on a real life example and we have to translate two versions of PRES+ models to FSMD models. Then using existing equivalence checker we have checked the equivalence between two FSMD models.

In this paper we focus on some aspects related to modeling and formal verification of embedded systems. Many models have been proposed to represent embedded systems. These models encompass a broad range of styles, characteristics, and application domains and include the extensions of finite state machines, data flow graphs, communication processes and Petri nets. In this report, we have used a PRES+ model (Petri net based Representation for Embedded Systems) as an extension of classical Petri net model that captures concurrency, timing behaviour of embedded systems; it allows systems to be representative in different levels of abstraction and improves expressiveness by allowing the token to carry information. Modeling using PRES+, as discussed above, may be convenient for specifying the input behaviour because it supports concurrency. However, there is no equivalence checking method reported in the literature for PRES+ models to the best of our knowledge. In contrast, equivalence checking of FSMD models exist. As a first step, therefore, we seek to devise an algorithm to translate PRES+ models to FSMD models and we seek to hand execute our algorithm on a real life example and we have to translate two versions of PRES+ models to FSMD models. Then using existing equivalence checker we have checked the equivalence between two FSMD models.

Cryptographic embedded systems are used to safeguard both access to classified data and controls for external subsystems. The assurance required for these systems extends beyond simply denying access to unauthorized users, hardware failures must not lead to the inadvertent activation of protected subcomponents or allow access to classified data. As more systems are transitioning from fixed hardware and state machine designs, for which more formalized failure type and rate calculations exist, there is an increasing need for this level of assurance for software-based processor systems in the absence of equivalent failure type and rate calculations for software. This paper presents a method to guarantee to a quantifiable level of confidence that external components are driven if-and-only-if an authenticated request is received. This is accomplished through the use of software algorithms, data storage formats, and analyzable comparator hardware detection and blocking logic.

In this paper, we investigate a radio frequency (RF) lens-embedded massive multiple-input multiple-output (MIMO) system and evaluate the system performance of limited feedback by utilizing a technique for generating a suitable codebook for the system. We fabricate an RF lens that operates on a 77 GHz (mmWave) band. Experimental results show a proper value of amplitude gain and an appropriate focusing property. In addition, using a simple numerical technique--beam propagation method (BPM)--we estimate the power profile of the RF lens and verify its accordance with experimental results. We also design a codebook--multi-variance codebook quantization (MVCQ)--for limited feedback by considering the characteristics of the RF lens antenna for massive MIMO systems. Numerical results confirm that the proposed system shows significant performance enhancement over a conventional massive MIMO system without an RF lens.

In this paper, we investigate a radio frequency (RF) lens-embedded massive multiple-input multiple-output (MIMO) system and evaluate the system performance of limited feedback by utilizing a technique for generating a suitable codebook for the system. We fabricate an RF lens that operates on a 77 GHz (mmWave) band. Experimental results show a proper value of amplitude gain and an appropriate focusing property. In addition, using a simple numerical technique--beam propagation method (BPM)--we estimate the power profile of the RF lens and verify its accordance with experimental results. We also design a codebook--multi-variance codebook quantization (MVCQ)--for limited feedback by considering the characteristics of the RF lens antenna for massive MIMO systems. Numerical results confirm that the proposed system shows significant performance enhancement over a conventional massive MIMO system without an RF lens.

In this paper, we investigate a radio frequency (RF) lens-embedded massive multiple-input multiple-output (MIMO) system and evaluate the system performance of limited feedback by utilizing a technique for generating a suitable codebook for the system. We fabricate an RF lens that operates on a 77 GHz (mmWave) band. Experimental results show a proper value of amplitude gain and an appropriate focusing property. In addition, using a simple numerical technique--beam propagation method (BPM)--we estimate the power profile of the RF lens and verify its accordance with experimental results. We also design a codebook--multi-variance codebook quantization (MVCQ)--for limited feedback by considering the characteristics of the RF lens antenna for massive MIMO systems. Numerical results confirm that the proposed system shows significant performance enhancement over a conventional massive MIMO system without an RF lens.

In this paper, we investigate a radio frequency (RF) lens-embedded massive multiple-input multiple-output (MIMO) system and evaluate the system performance of limited feedback by utilizing a technique for generating a suitable codebook for the system. We fabricate an RF lens that operates on a 77 GHz (mmWave) band. Experimental results show a proper value of amplitude gain and an appropriate focusing property. In addition, using a simple numerical technique--beam propagation method (BPM)--we estimate the power profile of the RF lens and verify its accordance with experimental results. We also design a codebook--multi-variance codebook quantization (MVCQ)--for limited feedback by considering the characteristics of the RF lens antenna for massive MIMO systems. Numerical results confirm that the proposed system shows significant performance enhancement over a conventional massive MIMO system without an RF lens.

Particle filtering methods are gradually attaining significant importance in a variety of embedded computer vision applications. For example, in smart camera systems, object tracking is a very important application and particle filter based tracking algorithms have shown promising results with robust tracking performance. However, most particle filters involve vast amount of computational complexity thereby intensifying the challenges faced in their real-time, embedded implementation. Many of these applications share common characteristics, and the same system design can be reused by identifying and varying key system parameters and varying them appropriately. In this paper, we present a System- on-Chip (SoC) architecture involving both hardware and software components for a class of particle filters. The framework uses parameterization to enable fast and efficient reuse of the architecture with minimal re-design effort for a wide range of particle filtering applications as well as implementation platforms. Using this framework, we explore different design options for implementing three different particle filtering applications on field-programmable gate arrays (FPGAs). The first two applications involve particle filters with one-dimensional state transition models, and are used to demonstrate the key features of the framework. The main focus of this paper is on design methodology for hardware/software implementation of multi-dimensional particle filter application and we explore this in the third application which is a 3D facial pose tracking system for videos. In this multi-dimensional particle filtering application, we extend our proposed architecture with models for hardware/software co-design so that limited hardware resources can be utilized most effectively. Our experiments demonstrate that the framework is easy and intuitive to use, while providing for efficient design and implementation.

Particle filtering methods are gradually attaining significant importance in a variety of embedded computer vision applications. For example, in smart camera systems, object tracking is a very important application and particle filter based tracking algorithms have shown promising results with robust tracking performance. However, most particle filters involve vast amount of computational complexity thereby intensifying the challenges faced in their real-time, embedded implementation. Many of these applications share common characteristics, and the same system design can be reused by identifying and varying key system parameters and varying them appropriately. In this paper, we present a System- on-Chip (SoC) architecture involving both hardware and software components for a class of particle filters. The framework uses parameterization to enable fast and efficient reuse of the architecture with minimal re-design effort for a wide range of particle filtering applications as well as implementation platforms. Using this framework, we explore different design options for implementing three different particle filtering applications on field-programmable gate arrays (FPGAs). The first two applications involve particle filters with one-dimensional state transition models, and are used to demonstrate the key features of the framework. The main focus of this paper is on design methodology for hardware/software implementation of multi-dimensional particle filter application and we explore this in the third application which is a 3D facial pose tracking system for videos. In this multi-dimensional particle filtering application, we extend our proposed architecture with models for hardware/software co-design so that limited hardware resources can be utilized most effectively. Our experiments demonstrate that the framework is easy and intuitive to use, while providing for efficient design and implementation.

Embedded systems are often subject to real-time constraints. Such systems require determinism to ensure that task deadlines are met. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines. Knowledge of bounds on worst-case execution times (WCET) of tasks is a critical piece of information required by schedulability analysis. Static timing analysis derives these bounds on WCETs, but requires that bounds on loop iterations be known statically, i.e., at compile time. This often limits the class of applications that may be analyzed by static timing analysis and, hence, used in a real-time system. Another limiting factor for real-time system design is the class of processors that may be used. Typically, modern, complex, processors may not be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks. The main reason is that these features introduce non-determinism to task execution, which can only be resolved at run-time. The contributions of this work are two-fold. First, we show how the constraint concerning statically bound loops may be relaxed and applied to make dynamic decisions at run-time to obtain power savings. Second, we introduce a new paradigm, which proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors. To the best of our knowledge, these methods of (a) using run-time information to obtain accurate upper bounds for loops and using that information to achieve energy savings, and (b) hardware/software interactions to calculate WCET results for out-of-order processors, are the first of their kind. ©2008 Microsoft Corporation. All rights reserved.

This thesis demonstrates a methodology to be used by a Program Manager to allow him to procedurally monitor the design development of an embedded weapons system. The methodology consists of a unique combination of several software engineering strategies integrated to form a powerful management tool. The primary objective of the methodology is to provide an algorithmic procedure which stresses simplicity at all levels of abstraction. Further, the system must be capable of generating good system specifications, good documentation, and fully understandable products. Sample products from the implementation of the methodology on the HARPOON Shipboard Command-Launch Control Set (HSCLCS) are provided for illustrative purposes. (Author)

This thesis demonstrates a methodology to be used by a Program Manager to allow him to procedurally monitor the design development of an embedded weapons system. The methodology consists of a unique combination of several software engineering strategies integrated to form a powerful management tool. The primary objective of the methodology is to provide an algorithmic procedure which stresses simplicity at all levels of abstraction. Further, the system must be capable of generating good system specifications, good documentation, and fully understandable products. Sample products from the implementation of the methodology on the HARPOON Shipboard Command-Launch Control Set (HSCLCS) are provided for illustrative purposes. (Author)

This contract has explored the multidimensional problem of the development of embedded software systems. In its reports and presentations the work has characterized these problems in various ways, but to view them as multidimensional is helpful inasmuch as the problems may be separated into different solution domains. These have been identified as: Communication; Principles and practices; Technology, and Compiler (Ada) language structure and capability. Contents: The Domain of Solutions; Integration of the Four Solution Domains; Tools; Program Architectural Designs; The Embedded Software Design Simulator (ESDS).

Project EOS is studying the problems of building adaptable real-time embedded operating systems for the scientific missions of NASA. Choices (A Class Hierarchical Open Interface for Custom Embedded Systems) is an operating system designed and built by Project EOS to address the following specific issues: the software architecture for adaptable embedded parallel operating systems, the achievement of high-performance and real-time operation, the simplification of interprocess communications, the isolation of operating system mechanisms from one another, and the separation of mechanisms from policy decisions. Choices is written in C++ and runs on a ten processor Encore Multimax. The system is intended for use in constructing specialized computer applications and research on advanced operating system features including fault tolerance and parallelism.

Project EOS is studying the problems of building adaptable real-time embedded operating systems for the scientific missions of NASA. Choices (A Class Hierarchical Open Interface for Custom Embedded Systems) is an operating system designed and built by Project EOS to address the following specific issues: the software architecture for adaptable embedded parallel operating systems, the achievement of high-performance and real-time operation, the simplification of interprocess communications, the isolation of operating system mechanisms from one another, and the separation of mechanisms from policy decisions. Choices is written in C++ and runs on a ten processor Encore Multimax. The system is intended for use in constructing specialized computer applications and research on advanced operating system features including fault tolerance and parallelism.

This thesis attempts to demonstrate the use of a combination of design method in the development of the Harpoon Weapon system. The initial design was presented in a thesis by Sentman and Maroney ADA126945. This thesis refines the initial design and presents a step by step process for designing a major system. Through the combination of many different techniques, the authors develop a unique logical approach to the software engineering problem associated with complex embedded weapons systems. Data flow diagrams are the first step. This approach allows the data or information to be charted throughout the system. A transform analysis is then performed on the data flow diagrams. This analysis imposes a control structure on the data and a hierarchical modular design is created. Once modules are identified, modules can then be grouped into packages to be used by Ada for a System Design Language or a Program Design Language.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace applications. Using the real-time programming techniques developed in co-operation with NASA in earlier research, the project staff is building a kernel for a multiple processor networked system. The first six months of the grant included a study of scheduling in an object-oriented system, the design philosophy of the kernel, and the architectural overview of the operating system. In this report, the operating system and kernel concepts are described. An environment for the experiments has been built and several of the key concepts of the system have been prototyped. The kernel and operating system is intended to support future experimental studies in multiprocessing, load-balancing, routing, software fault-tolerance, distributed data base design, and real-time processing.

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This project aims to develop a comprehensive approach to the model-based design of high-confidence distributed embedded systems. We will take advantage and fully leverage a shared theoretical foundation and technology infrastructure in four focus areas: hybrid and embedded systems theory, model-based software design, composable tool architectures and experimental testbeds. The objectives of our research in the focus areas are the following: (1) Develop theory of deep composition of hybrid systems with attributes of computational and communication platforms. (2) Develop foundations of model-based software design for high-confidence, networked embedded systems applications. (3) Develop composable tool architecture that supports high-level reusability of modeling, model-analysis, verification and testing tools in domain-specific tool chains. (4) Demonstrate the overall effort by creating an end-to-end design tool chain prototype for the model-based generation and verification of embedded controller code for experimental platforms.

This project aims to develop a comprehensive approach to the model-based design of high-confidence distributed embedded systems. We will take advantage and fully leverage a shared theoretical foundation and technology infrastructure in four focus areas: hybrid and embedded systems theory, model-based software design, composable tool architectures and experimental testbeds. The objectives of our research in the focus areas are the following: (1) Develop theory of deep composition of hybrid systems with attributes of computational and communication platforms. (2) Develop foundations of model-based software design for high-confidence, networked embedded systems applications. (3) Develop composable tool architecture that supports high-level reusability of modeling, model-analysis, verification and testing tools in domain-specific tool chains. (4) Demonstrate the overall effort by creating an end-to-end design tool chain prototype for the model-based generation and verification of embedded controller code for experimental platforms.

User training on computer-aided design (CAD) systems traditionally has been expensive and ineffective. In addition, rapid changes in CAD software demand frequent update instruction to be able to take full advantage of the system's capabilities. As the U.S. army Corps of Engineers begins using CAD technology to an increasing degree, there is a great need for low-cost, effective teaching programs. Embedded instruction programs represent a promising answer to this need. This technology involves the incorporation of tutorial programs directly into the software being taught, with the software used to drive the training session. Such a teaching method allows users to participate in self-paced study on the system they will be using in actual day-to-day operations. The U.S. Army Construction Engineering Research Laboratory (USE-CERL) has developed and tested an embedded instruction program for teaching CAD. The Program was demonstrated in a field test funded under the Technology Transfer Test Bed program. The field test results indicate that architects and engineers profit from online instruction embedded in the CAD system that they are learning. There is wide variability in the time spent studying the lessons as well as in learning strategies employed by different students. Follow-up questionnaires revealed a preference for this type of instruction over traditional methods.

Presentation on design space exploration and optimization of embedded cache systems via a compiler.

In this paper, using of automotive use cases as benchmarks for real-time system design has been proposed. The use cases are described in a format supported by AMALTHEA platform, which is a model based open source development environment for automotive multi-core systems. An example of a simple Electronic Control Unit has been analysed and presented with enough details to reconstruct this system in any format. For researchers willing to use AMALTHEA file format directly, an appropriate parser has been developed and offered. An example of applying this parser and benchmark for optimising makespan while not violating the timing constraints by allocating functionality to different Network on Chip resource is demonstrated.

In this paper, using of automotive use cases as benchmarks for real-time system design has been proposed. The use cases are described in a format supported by AMALTHEA platform, which is a model based open source development environment for automotive multi-core systems. An example of a simple Electronic Control Unit has been analysed and presented with enough details to reconstruct this system in any format. For researchers willing to use AMALTHEA file format directly, an appropriate parser has been developed and offered. An example of applying this parser and benchmark for optimising makespan while not violating the timing constraints by allocating functionality to different Network on Chip resource is demonstrated.

Due to the nature of the algorithms typically employed in applications such as STAP, sensor data fusion, and target detection, it was decided to integrate the signal processing areas of space time adaptive processing and signal detection. In particular, the following algorithms were parallelized: (1) AFRL (Rome) version of a PEI staggered post-Doppler STAP algorithm. This algorithm, comprised of more than 23,000 lines of code, included the steps of (a) Doppler filter processing, (b) weight computation, (c) beam forming, (d) pulse compression, and (e) constant false alarm rate (CFAR) processing. (2) Ozturk (clutter characterization) algorithm. This algorithm is used to analyze random data and includes the steps of (a) goodness of fit test and (b) probability distribution approximation. (3) Ordered statistic CFAR algorithm. This CFAR algorithm is in addition to the cell averaging CFAR algorithm contained in the PRI staggered post-Doppler STAP algorithm. In carrying out the algorithm parallelizations, the following tasks/technical requirements were accomplished: (1) Efficient techniques for high speed, high volume I/O applicable to embedded high performance systems were designed and implemented. (2) Data distribution and redistribution strategies for both inter-task and intra-task data communications in real time pipelined and parallelized applications were designed and implemented. (3) A documented beta code release was implemented to illustrate the full system with all major functional, technical, programming, documentation, installation, and user application features to be included in the full delivery. (4) The individual algorithms, as well as the integrated applications, were implemented, demonstrated, benchmarked, and evaluated on the Intel Parago and, IBM SP2.

Due to the nature of the algorithms typically employed in applications such as STAP, sensor data fusion, and target detection, it was decided to integrate the signal processing areas of space time adaptive processing and signal detection. In particular, the following algorithms were parallelized: (1) AFRL (Rome) version of a PEI staggered post-Doppler STAP algorithm. This algorithm, comprised of more than 23,000 lines of code, included the steps of (a) Doppler filter processing, (b) weight computation, (c) beam forming, (d) pulse compression, and (e) constant false alarm rate (CFAR) processing. (2) Ozturk (clutter characterization) algorithm. This algorithm is used to analyze random data and includes the steps of (a) goodness of fit test and (b) probability distribution approximation. (3) Ordered statistic CFAR algorithm. This CFAR algorithm is in addition to the cell averaging CFAR algorithm contained in the PRI staggered post-Doppler STAP algorithm. In carrying out the algorithm parallelizations, the following tasks/technical requirements were accomplished: (1) Efficient techniques for high speed, high volume I/O applicable to embedded high performance systems were designed and implemented. (2) Data distribution and redistribution strategies for both inter-task and intra-task data communications in real time pipelined and parallelized applications were designed and implemented. (3) A documented beta code release was implemented to illustrate the full system with all major functional, technical, programming, documentation, installation, and user application features to be included in the full delivery. (4) The individual algorithms, as well as the integrated applications, were implemented, demonstrated, benchmarked, and evaluated on the Intel Parago and, IBM SP2.

Due to the nature of the algorithms typically employed in applications such as STAP, sensor data fusion, and target detection, it was decided to integrate the signal processing areas of space time adaptive processing and signal detection. In particular, the following algorithms were parallelized: (1) AFRL (Rome) version of a PEI staggered post-Doppler STAP algorithm. This algorithm, comprised of more than 23,000 lines of code, included the steps of (a) Doppler filter processing, (b) weight computation, (c) beam forming, (d) pulse compression, and (e) constant false alarm rate (CFAR) processing. (2) Ozturk (clutter characterization) algorithm. This algorithm is used to analyze random data and includes the steps of (a) goodness of fit test and (b) probability distribution approximation. (3) Ordered statistic CFAR algorithm. This CFAR algorithm is in addition to the cell averaging CFAR algorithm contained in the PRI staggered post-Doppler STAP algorithm. In carrying out the algorithm parallelizations, the following tasks/technical requirements were accomplished: (1) Efficient techniques for high speed, high volume I/O applicable to embedded high performance systems were designed and implemented. (2) Data distribution and redistribution strategies for both inter-task and intra-task data communications in real time pipelined and parallelized applications were designed and implemented. (3) A documented beta code release was implemented to illustrate the full system with all major functional, technical, programming, documentation, installation, and user application features to be included in the full delivery. (4) The individual algorithms, as well as the integrated applications, were implemented, demonstrated, benchmarked, and evaluated on the Intel Parago and, IBM SP2.

We introduce a new platform for realizing on-chip quantum electrodynamics using photonic crystal waveguide structures comprised of periodic nanowire arrays with embedded semiconductor quantum dots to act as quantum light sources. These nanowire-based structures, which can now be fabricated with excellent precision, are found to produce waveguide Purcell factors exceeding 100 and on-chip beta factors up to 99%. We investigate the fundamental optical properties of photonic crystal waveguides and finite-size structures using both photonic band structure calculations and rigorous Green function computations which allows us to obtain the modal properties and the local density of photon states. A comparison with slab-based photonic crystals is also made and we a highlight key advantages in the nanowire system, including the potential to minimize extrinsic scattering losses and produce high theoretical Purcell factors and beta-factors on-chip. We also demonstrate that these structures exhibit rich photonic Lamb shifts over broadband frequencies.

We introduce a new platform for realizing on-chip quantum electrodynamics using photonic crystal waveguide structures comprised of periodic nanowire arrays with embedded semiconductor quantum dots to act as quantum light sources. These nanowire-based structures, which can now be fabricated with excellent precision, are found to produce waveguide Purcell factors exceeding 100 and on-chip beta factors up to 99%. We investigate the fundamental optical properties of photonic crystal waveguides and finite-size structures using both photonic band structure calculations and rigorous Green function computations which allows us to obtain the modal properties and the local density of photon states. A comparison with slab-based photonic crystals is also made and we a highlight key advantages in the nanowire system, including the potential to minimize extrinsic scattering losses and produce high theoretical Purcell factors and beta-factors on-chip. We also demonstrate that these structures exhibit rich photonic Lamb shifts over broadband frequencies.

IPChinook is a design tool for distributed embedded systems. It gains leverage from the use of a carefully chosen set of design abstractions that raise the level of designer interaction during the specification, synthesis, and simulation of the design. IPChinook focuses On a component-based approach to system building that enhances the ability to reuse existing software modules. This is accomplished through a new model for constructing components that enables composition of control-flow as well as data-flow. The designer then maps the elements of die specification to a target architecture: a set of processing elements and communication channels IPChinook synthesizes all of the detailed communication and synchronization instructions. Designers get feedback via a co-simulation engine that permits rapid evaluation. By shortening the design cycle, designers are able to more completely explore the design space of possible architectures and/or improve time-to-market. IPChinook is embodied in a system development environment that supports the design methodology by integrating a user interface for system specification, simulation, and synthesis tools. By raising the level of abstraction of specifications above die low-level target-specific implementation, and by automating the generation of these difficult and error-prone details, IPChinook lets designers focus on global architectural and functionality decisions.

IPChinook is a design tool for distributed embedded systems. It gains leverage from the use of a carefully chosen set of design abstractions that raise the level of designer interaction during the specification, synthesis, and simulation of the design. IPChinook focuses On a component-based approach to system building that enhances the ability to reuse existing software modules. This is accomplished through a new model for constructing components that enables composition of control-flow as well as data-flow. The designer then maps the elements of die specification to a target architecture: a set of processing elements and communication channels IPChinook synthesizes all of the detailed communication and synchronization instructions. Designers get feedback via a co-simulation engine that permits rapid evaluation. By shortening the design cycle, designers are able to more completely explore the design space of possible architectures and/or improve time-to-market. IPChinook is embodied in a system development environment that supports the design methodology by integrating a user interface for system specification, simulation, and synthesis tools. By raising the level of abstraction of specifications above die low-level target-specific implementation, and by automating the generation of these difficult and error-prone details, IPChinook lets designers focus on global architectural and functionality decisions.