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As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectures require new methods for high-level application mapping and hardware/software codesign. In this paper, we present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing applications. That is, we seek to synthesize an application-specific interconnect topology. We show that flexible interconnect topologies utilizing low-hop communication between processors offer advantages for reduced power and latency. We show that existing multiprocessor scheduling algorithms can deadlock if the topology graph is not strongly connected, or if a constraint is imposed on the maximum number of hops allowed for communication. We detail an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock. We show that it is advantageous to perform application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm that utilizes graph isomorphism to pare the design space.

Embedded systems are distinguished from general-purpose computers in that they consist of special-purpose hardware and software optimized for a specific task. They are pervasive in Army systems, appearing in soldier radios, sensor systems, vehicle control, communication systems, and many other applications. This paper focuses on multiprocessor embedded systems targeted towards signal, image, and video processing applications requiring large computing power and having real-time performance requirements. As transistor sizes shrink, interconnects represent a significant bottleneck for embedded systems designers. Several groups are researching optical interconnects to cope with this trend. Optical interconnects enable new system architectures. These new architectures in turn require new methods for high-level application mapping and hardware/software co-design. In this presentation, we discuss high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessors. We focus on designs that are streamlined for one or more digital signal processing (DSP) applications. That is, we seek to synthesize an application specific interconnect topology for a multiprocessor DSP design. We show that flexible interconnect topologies that allow single-hop communication between processors offer advantages for reduced power and latency.

Several trends in technology have important implications for future digital signal processing (DSP) systems. By the year 2010, integrated circuit technology will allow 800 million transistors on a single chip. Already, manufacturers are placing multiple DSP cores on a single chip. Multiprocessor systems will become increasingly important in the future. A significant challenge is to develop software and compiler techniques to effectively exploit multiple processors. Signal and image processing algorithms are among those applications that can benefit from multiprocessor systems. Optics provides unique advantages and opportunities for designers of embedded multiprocessor systems, including the ability to construct highly connected and irregular networks that are streamlined for particular applications. Using these networks, it is possible to implement application mappings that allow flexible, low-hop communication patterns between processors. This has advantages for reduced system latency and power. Such optically connected multiprocessors are particularly promising for embedded DSP applications, which are highly parallel, and typically have tight constraints on latency and power consumption. Several groups have demonstrated optically-connected multiprocessor systems. However, comparatively little work has been done to develop compiler technology and automated mapping tools to take advantage of these systems. This work addresses the co-design of interconnect topologies and application mappings for DSP systems on optically connected multiprocessors. We demonstrate that existing DSP scheduling algorithms will deadlock for arbitrarily-connected networks, or when communication is restricted to a limited number of hops. We show that these low-hop communication schedules produce low power and low latency mappings.

This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are non-negligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and non-iterative execution. We develop new heuristics for finding efficient transaction orders, and perform an experimental comparison to gauge the performance of these heuristics.

All real time tasks which are termed as critical tasks by nature have to complete its execution before its deadline, even in presence of faults. The most popularly used real time task assignment algorithms are First Fit (FF), Best Fit (BF), Bin Packing (BP).The common task scheduling algorithms are Rate Monotonic (RM), Earliest Deadline First (EDF) etc.All the current approaches deal with either fault tolerance or criticality in real time. In this paper we have proposed an integrated approach with a new algorithm, called SASA (Sorting And Sequential Assignment) which maps the real time task assignment with task schedule and fault tolerance

As transistor sizes shrink and we approach the end of Moore's law interconnects-both on-chip and off-chip-will represent the biggest bottleneck for embedded systems designers. Several groups are researching optical interconnects to cope with this tread. Optical interconnects enable new system architectures. These new architectures in turn require new methods for high-level application mapping and hardware/software co-design. In this presentation, we discuss high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessors. We focus on designs that are streamlined for one or more digital signal processing (DSP) applications. That is, we seek to synthesize an application-specific interconnect topology for a multiprocessor DSP design. We show that flexible interconnect topologies that allow single- hop communication between processors offer advantages for reduced power and latency. We have previously shown that multiprocessor scheduling algorithms can deadlock in the general case of a topology graph that is not strongly connected or if communication is limited to be single hop. We have also demonstrated an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock 1. In this presentation we discuss the advantages of performing application scheduling and interconnect synthesis jointly and present a probabilistic scheduling/ interconnect algorithm utilizing graph isomorphism to pare the design space. We demonstrate the performance advantages that an application-specific interconnect topology can produce for several DSP beachmarks.

This paper explores the problem of efficiently ordering interprocessor communication operations in both statically and dynamically-scheduled multiprocessors for iterative dataflow graphs with probabilistic execution times. In most digital signal processing applications, the throughput of the system is significantly affected by communication costs. We explicitly model these costs within an effective graph-theoretic analysis framework. We show that ordered transaction schedules can significantly outperform both self-timed schedules and dynamic schedules for moderate task execution time variability. As the task execution time variability increases, we show that first selftimed and then dynamic scheduling policies are preferred. We perform an extensive experimental comparison on both real and simulated benchmarks to gauge the effect of synchronization and communication overhead costs on these crossover points.