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We present TRI\`EST, a suite of one-pass streaming algorithms to compute unbiased, low-variance, high-quality approximations of the global and local (i.e., incident to each vertex) number of triangles in a fully-dynamic graph represented as an adversarial stream of edge insertions and deletions. Our algorithms use reservoir sampling and its variants to exploit the user-specified memory space at all times. This is in contrast with previous approaches which use hard-to-choose parameters (e.g., a fixed sampling probability) and offer no guarantees on the amount of memory they will use. We show a full analysis of the variance of the estimations and novel concentration bounds for these quantities. Our experimental results on very large graphs show that TRI\`EST outperforms state-of-the-art approaches in accuracy and exhibits a small update time.

Datasheet for a 4116 16K × 1 bit dynamic RAM. First published 1977-10. Revised 1985-11.

Cloud is a new age technology used to connect to applications and data from anywhere round the globe via the internet. Anything and everything ranging from mobile phones to servers can be connected to the cloud. This has resulted into companies providing a large range of services to consumers. Upcoming businesses can now focus on its major purpose and not have to install their own servers. They can easily outsource it to these cloud providers saving them from a lot of capital investment. With the ever increasing devices on the cloud a major issue has emerged, something that needs immediate attention - Resource utilization. All the resources connected to the cloud need to function optimally for making cloud providers earn proper Return on Investment (RoI) and making the cloud users experience worthwhile. This paper proposes a new Resource Allocation Strategy for provisioning of virtual machines (VM). This work focuses on two phases, firstly the initial allocation of VMs using K-Mean Clustering technique and secondly on maximizing the optimal functioning of these VMs by migrating them from one physical machine (PM) to another. For this purpose the Load Balancing Algorithm, Skewness Algorithm and the Green Computing Algorithm are used. It also introduces a change in the Load Balancing Equation and the Skewness Equation which gives much better results.

Pointers in C++ Programming with Dynamic Memory Allocations

Preregistration of Secondary Data Analysis. See the attached Preregistration Form for more details including references.

From the bitsavers.org collection, a scanned-in computer-related document. motorola :: VME :: MVME202 222 :: MVME202 D1 512KB 1MB 2MB Dynamic Memory Users Manual Aug84

From the bitsavers.org collection, a scanned-in computer-related document. motorola :: VME :: MVME202 222 :: MVME202 D1 512KB 1MB 2MB Dynamic Memory Users Manual Aug84

From the bitsavers.org collection, a scanned-in computer-related document. motorola :: VME :: MVME202 222 :: MVME202 D1 512KB 1MB 2MB Dynamic Memory Users Manual Aug84

Previous studies have demonstrated that gaze bias reflects internal selection in working memory (WM). In this study, we aim to explore the functional significance of gaze bias. Specifically, we investigate whether the purpose of gaze bias during WM selection is to enhance the selection of the target, mitigate confusion from the distractor, or both. Additionally, we attempt to decode the dynamic processes of WM selection and retrieval from the geometric patterns of gaze.

Buy the book: http://www.ibmpressbooks.com/bookstore/product.asp?isbn=9780132755108 Kevin Maney, one of the authors of Making the World Work Better, tells the story of Bob Dennard's epiphany about storing information by putting charge on a capacitor.

Perma.cc archive of https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiPiIyejaX6AhX3hYkEHemhCScQFnoECAcQAQ&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FDynamic_random-access_memory&usg=AOvVaw3InZ7-qrM0IdfI0ce-G0Cb created on 2022-09-21 05:07:32.457189+00:00.

Humans are endowed with the fascinating ability to mentally travel in time. This faculty allows them, among other things, to mentally relive episodes from their personal past (D’Argembeau, 2020). However, remembering an event is not like replaying a continuous video recording but instead involves a sequence of experience units (EUs)—each unit representing a moment of the past experience—that are separated by temporal discontinuities (i.e., moments that are not remembered) (D’Argembeau et al., 2022). Because of these discontinuities, the time taken to mentally re-experience everyday activities is typically shorter than their actual duration, a phenomenon referred to as the temporal compression of events in episodic memory (Jeunehomme et al., 2018; Jeunehomme & D’Argembeau, 2019). However, the cognitive mechanisms leading to this structure of episodic memories are not fully understood, especially factors that explain temporal discontinuities. A consistent body of work suggests that EUs are formed through cognitive processing taking place during event perception. In daily life, we constantly segment the continuous flow of experience into meaningful units (i.e., events) that are temporally delimited by the perception of event boundaries (i.e., the end of an event and the beginning of another) (Kurby & Zacks, 2008; Radvansky & Zacks, 2017; Zacks, 2020). Between event boundaries, working memory enables us to construct and maintain a mental model of the current situation (i.e., an event model) while continuously processing incoming information (Loschky et al., 2020; Radvansky & Zacks, 2017; Trapp et al., 2021). When the situation changes (i.e., when an event boundary is perceived), the current event model is updated and its previous version is integrated in the long-term memory representation of the ongoing sequence of events (Bird, 2020). Based on this work on event segmentation, we suggest that temporal discontinuities within episodic memories is a byproduct of the role of working memory in constructing event models. When new information needs to be continuously processed, working memory capacity is temporally limited: without rehearsal, the information just perceived is only maintained for a limited amount of time (Barrouillet et al., 2004). So, in the context of event model formation, the capacity limit of working memory (i.e., the time during which information can be held in working memory without active rehearsal) should correspond to the maximal duration of an event model that can be fully maintained in mind. When this temporal capacity is exceeded before the perception of an event boundary, the EU formed at the end of the current event would only partially represent its unfolding. It follows that temporal discontinuities in long-term memory representations of past experience should depend on the number of events they integrate and their actual duration. The present study aims to test this hypothesis by examining how the number and duration of events to remember influence mental replay time. To address this question, we will measure the time taken by participants to mentally replay short movies depicting 1, 2, or 3 events (without event boundaries), each lasting 3, 6, 9, or 12 seconds.

Everyday life unfolds continuously, but somehow our memories are more discrete and episodic, broken down into individual memories or events. Increasing research suggests that continuity and change in an unfolding context (e.g., spatial location) promotes the transformation of ongoing experiences into distinct and memorable events (Clewett et al., 2019). To date, much of the research on this idea has focused on how stability and change in the external environment (e.g., remaining within a room and then crossing into a new one) affects the organization of episodic memory. But everyday life is also heavily colored by dynamic fluctuations in emotional experiences and moods. Somewhat surprisingly, even though it is well established that emotional stimuli have an especially strong influence on cognitive processing, little work has taken a holistic approach to understanding how emotion simultaneously impacts the multi-faceted elements of memory (e.g., space, time, perceptual features, subjective feelings; see Clewett and Murty, 2019; Palombo and Cocquyt, 2020). The goal of this study is to examine how music induces discrete and lingering effects on emotional states, and how these mood fluctuations in turn affect different aspects of memory for temporally-extended sequences. Recent evidence shows that fluctuations in arousal states, as indexed by pupil size and dilation, predict the temporal integration of sequential information in memory (Clewett et al., 2020). This suggests that dynamic musical pieces and the moods they induce can influence how information is integrated together. Another possibility is that emotional stimuli function as especially strong context shifts during dynamic experiences, because they elicit much more robust increases in arousal than neutral information (Clewett et al., 2020). Motivated by these findings, we plan to investigate how emotional states that unfold during neutral item sequences elicit discrete and sustained effects on encoding temporal, perceptual, and event information. Specifically, we will examine how emotional contexts, elicited through controlled-musical stimuli, influence different aspects of episodic memory representations, including memory for temporal order, temporal distance, individual items representations, and temporal source context.

Everyday life unfolds continuously, but somehow our memories are more discrete and episodic, broken down into individual memories or events. Increasing research suggests that continuity and change in an unfolding context (e.g., spatial location) promotes the transformation of ongoing experiences into distinct and memorable events (Clewett et al., 2019). To date, much of the research on this idea has focused on how stability and change in the external environment (e.g., remaining within a room and then crossing into a new one) affects the organization of episodic memory. But everyday life is also heavily colored by dynamic fluctuations in emotional experiences and moods. Somewhat surprisingly, even though it is well established that emotional stimuli have an especially strong influence on cognitive processing, little work has taken a holistic approach to understanding how emotion simultaneously impacts the multi-faceted elements of memory (e.g., space, time, perceptual features, subjective feelings; see Clewett and Murty, 2019; Palombo and Cocquyt, 2020). The goal of this study is to examine how music induces discrete and lingering effects on emotional states, and how these mood fluctuations in turn affect different aspects of memory for temporally-extended sequences. Recent evidence shows that fluctuations in arousal states, as indexed by pupil size and dilation, predict the temporal integration of sequential information in memory (Clewett et al., 2020). This suggests that dynamic musical pieces and the moods they induce can influence how information is integrated together. Another possibility is that emotional stimuli function as especially strong context shifts during dynamic experiences, because they elicit much more robust increases in arousal than neutral information (Clewett et al., 2020). Motivated by these findings, we plan to investigate how emotional states that unfold during neutral item sequences elicit discrete and sustained effects on encoding temporal, perceptual, and event information. Specifically, we will examine how emotional contexts, elicited through controlled-musical stimuli, influence different aspects of episodic memory representations, including memory for temporal order, temporal distance, individual items representations, and temporal source context.

This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM array of eight four-bit words including refresh circuitry. In the last several years, there has been significant research investigating the possibilities of producing much faster, lower power and high density DRAM using GaAs. Thus far, this research has yielded success on a limited basis using special materials and fabrication techniques. This design, tested and simulated using HSPICE, supports a memory access time of approximately three nanoseconds, faster than present commercial Static Random Access Memory (SRAM). The logic circuits are designed using GaAs enhancement-mode and depletion-mode (E/ D) metal semiconductor field-effect transistors (MESFETs). Charge storage is facilitated by a single GaAs MESFET connected to a parallel plate capacitor and the required minimum time between refresh is approximately three milliseconds. Power consumption is acceptable and fabrication by Vitesse Semiconductor Corporation using the HGaAs3 process is in progress. The design techniques, power consumption and timing are discussed and demonstrated for the basic logic circuits and the memory array read, write and refresh cycles. A significant increase in DRAM memory bandwidth is gained narrowing the memory bandwidth differential between primary memory and the processor.

The results of Study 2 supported that the purpose of gaze bias during WM selection is solely to enhance the selection of the target, without mitigating confusion from the distractor. In Study 3, we aimed to explore a potential alternative explanation for this finding. Specifically, within the setting of Study 2, a gaze biased to the target will be unavoidable away from the distractor, since the target and distractor are positioned in opposite directions from the initial gaze position. In this study, we aimed to examine whether gaze bias serves the function of escaping the distractor more rigorously. We replaced a WM item with a pre-learned long-term memory (LTM) colored bar, which does not induce WM selection or the corresponding gaze bias. Consequently, when the LTM item serves as the target, no bias away from the distractor will be induced during retrieval of the LTM item to aid in the completeness of escaping the distractor. If gaze bias serves the function of mitigating confusion from the distractor, we expect to observe a stronger gaze bias away from the WM distractor when the WM distractor is closer.

Modern embedded processors include both scratchpad memory (SPM) and cache memory in their architectures. SPM's are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection (SEC-DED) and SEC-DED double-adjacent error correction (SEC-DED-DAEC) and parity duplication approach. These approaches are used only error correction for less number of corrections and thus increases speed. This paper proposes a duplication scheme, cache-assisted duplicated SPM(CADS) to correct SEUs and SEMUs in data SPM lines detected by a low-cost error detecting code. This duplication approach does error detection in SPM which is faster than ECC providing multibit error correction. The extension is to include DMA with ring descriptors. The descriptor-based model provides the most flexibility in managing a system's DMA faster data transfers to or from Scratchpad memory. Asapu Harika | Mr. A. Sai Kumar Goud | Mr. Pradeep Kumar Reddy"A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14351.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14351/a-dynamic-scratchpad-memory-collaborated-with-cache-memory-for-transferring-data-for-multi-bit-error-correction/asapu-harika

Cloud computing relies on secure and efficient virtualization. Software level security solutions compromise the performance of virtual machines (VMs), as a large amount of computational power would be utilized for running the security modules. Moreover, software solutions are only as secure as the level that they work on. For example a security module on a hypervisor cannot provide security in the presence of an infected hypervisor. It is a challenge for virtualization technology architects to enhance the security of VMs without degrading their performance. Currently available server machines are not fully equipped to support a secure VM environment without compromising on performance. A few hardware modifications have been introduced by manufactures like Intel and AMD to provide a secure VM environment with low performance degradation. In this paper we propose a novel memory architecture model named \textit{ Architectural Support for Memory Isolation(ASMI)}, that can achieve a true isolated physical memory region to each VM without degrading performance. Along with true memory isolation, ASMI is designed to provide lower memory access times, better utilization of available memory, support for DMA isolation and support for platform independence for users of VMs.

The read channel in Flash memory systems degrades over time because the Fowler-Nordheim tunneling used to apply charge to the floating gate eventually compromises the integrity of the cell because of tunnel oxide degradation. While degradation is commonly measured in the number of program/erase cycles experienced by a cell, the degradation is proportional to the number of electrons forced into the floating gate and later released by the erasing process. By managing the amount of charge written to the floating gate to maintain a constant read-channel mutual information, Flash lifetime can be extended. This paper proposes an overall system approach based on information theory to extend the lifetime of a flash memory device. Using the instantaneous storage capacity of a noisy flash memory channel, our approach allocates the read voltage of flash cell dynamically as it wears out gradually over time. A practical estimation of the instantaneous capacity is also proposed based on soft information via multiple reads of the memory cells.

From the bitsavers.org collectio n, a scanned-in computer-related document. amd :: dataBooks :: 1981 AMD Am2960 Series Dynamic Memory Support Handbook

From the bitsavers.org collection, a scanned-in computer-related document. vectorGraphic :: Vector 48K Dynamic Memory Board Feb79

Includes bibliographical references (p. 355-360) and index

Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3% - 7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP.

In this paper we have proposed an adaptive dynamic cache replacement algorithm for a multimedia servers cache system. The goal is to achieve an effective utilization of the cache memory which stores the prefix of popular videos. A replacement policy is usually evaluated using hit ratio, the frequency with which any video is requested. Usually discarding the least recently used page is the policy of choice in cache management. The adaptive dynamic replacement approach for prefix cache is a self tuning, low overhead algorithm that responds online to changing access patterns. It constantly balances between lru and lfu to improve combined result. It automatically adapts to evolving workloads. Since in our algorithm we have considered a prefix caching with multicast transmission of popular objects it utilizes the hard disk and network bandwidth efficiently and increases the number of requests being served.

This article is from Frontiers in Behavioral Neuroscience , volume 8 . Abstract Mammalian memory is the result of the interaction of millions of neurons in the brain and their coordinated activity. Candidate mechanisms for memory are synaptic plasticity changes, such as long-term potentiation (LTP). LTP is essentially an electrophysiological phenomenon manifested in hours-lasting increase on postsynaptic potentials after synapse tetanization. It is thought to ensure long-term changes in synaptic efficacy in distributed networks, leading to persistent changes in the behavioral patterns, actions and choices, which are often interpreted as the retention of information, i.e., memory. Interestingly, new neurons are born in the mammalian brain and adult hippocampal neurogenesis is proposed to provide a substrate for dynamic and flexible aspects of behavior such as pattern separation, prevention of interference, flexibility of behavior and memory resolution. This work provides a brief review on the memory and involvement of LTP and adult neurogenesis in memory phenomena.

Preregistration for an experiment testing whether the way in which people segment dynamic maps influences their memory for the temporal order of the events in the map.

A virtual memory is a hierarchial or multi-level memory with an address mapping mechanism and an allocation algorithm. The first level of the hierarchy is the primary memory. The primary memory has the highest speed and smallest capacity in the hierarchy. Subsequent levels have decreasing speed and increasing storage capacity. The addressing mechanism maps a program's address space into the physical memory space. The address space of the program can be much larger than the available capacity of the primary memory. For this thesis, a page-oriented addressing mechanism was employed. A page is a fixed size block of computer words associated with contiguous memory addresses. The allocation algorithm manages the flow of pages to and from the primary memory.

This article is from BMC Neuroscience , volume 15 . Abstract None

We study a generalization of the classic paging problem that allows the amount of available memory to vary over time - capturing a fundamental property of many modern computing realities, from cloud computing to multi-core and energy-optimized processors. It turns out that good performance in the "classic" case provides no performance guarantees when memory capacity fluctuates: roughly speaking, moving from static to dynamic capacity can mean the difference between optimality within a factor 2 in space and time, and suboptimality by an arbitrarily large factor. More precisely, adopting the competitive analysis framework, we show that some online paging algorithms, despite having an optimal (h,k)-competitive ratio when capacity remains constant, are not (3,k)-competitive for any arbitrarily large k in the presence of minimal capacity fluctuations. In this light it is surprising that several classic paging algorithms perform remarkably well even if memory capacity changes adversarially - even without taking those changes into explicit account! In particular, we prove that LFD still achieves the minimum number of faults, and that several classic online algorithms such as LRU have a "dynamic" (h,k)-competitive ratio that is the best one can achieve without knowledge of future page requests, even if one had perfect knowledge of future capacity fluctuations (an exact characterization of this ratio shows it is almost, albeit not quite, equal to the "classic" ratio k/(k-h+1)). In other words, with careful management, knowing/predicting future memory resources appears far less crucial to performance than knowing/predicting future data accesses.

Employing the Ginzburg-Landau phase-field theory, a new coupled dynamic thermo-mechanical 3D model has been proposed for modeling the cubic-to-tetragonal martensitic transformations in shape memory alloy (SMA) nanostructures. The stress-induced phase transformations and thermo-mechanical behavior of nanostructured SMAs have been investigated. The mechanical and thermal hysteresis phenomena, local non-uniform phase transformations and corresponding non-uniform temperature and deformations distributions are captured successfully using the developed model. The predicted microstructure evolution qualitatively matches with the experimental observations. The developed coupled dynamic model has provided a better understanding of underlying martensitic transformation mechanisms in SMAs, as well as their effect on the thermo-mechanical behavior of nanostructures.

Recent studies have shown a number of surprising vortex dynamics phenomena both in low and high temperature superconductors, which include: low frequency noise, slow voltage oscillations, history dependent dynamic response, memory of the direction, amplitude, duration, and frequency of the previously applied current, suppression of a large ac vortex response by a very small dc bias, and a strong frequency dependence. Taken together, these phenomena are incompatible with the current understanding of bulk vortex dynamics. We propose a generic mechanism to account for these observations in terms of the competition between the injection of a disordered vortex phase through the surface barriers at the sample edges, and the annealing of this metastable disorder by the transport current. The model is confirmed by investigating the current distribution across NbSe2 single crystals using arrays of Hall sensors. For an ac current only narrow regions near the edges are in the pinned disordered phase resulting in a large response. In the presence of a dc bias a wide region of the sample is filled by the disordered phase preventing vortex motion. The resulting spatial variation of the disorder across the sample acts as an active memory of the previously applied current sequence.

The complementarity of the liquid and plasma descriptions of the classical one-component plasma (OCP) is explored by studying wavevector and frequency dependent dynamical quantities: the dynamical structure factor (DSF), and the dynamic local field correction (LFC). Accurate Molecular Dynamics (MD) simulations are used to validate/test models of the DSF and LFC. Our simulations, which span the entire fluid regime ($\Gamma = 0.1 - 175$), show that the DSF is very well represented by a simple and well known memory function model of generalized hydrodynamics. On the other hand, the LFC, which we have computed using MD for the first time, is not well described by existing models.

This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.

From the bitsavers.org collection, a scanned-in computer-related document. components :: amd :: dataBooks :: 1990 AMD Dynamic Memory Design Handbook and Data Book

From the bitsavers.org collection, a scanned-in computer-related document. vmeSpecialists :: VMESpecialists DRAM512-D 512K 2MB VME Dynamic Memory Module 1985

டைனமிக் மெமரி இங்கிலீஷ் ஸ்பிக்கீங்க் கோர்ஸ்

We propose a scheme to dynamically realize a quantum memory based on the toric code. The code is generated from qubit systems with typical two-body interactions (Ising, XY, Heisenberg) using periodic, NMR-like, pulse sequences. It allows one to encode the logical qubits without measurements and to protect them dynamically against the time evolution of the physical qubits. A weakly coupled cavity mode mediates a long-range attractive interaction between the stabilizer operators of the toric code, thereby suppressing the creation of thermal anyons. This significantly increases the lifetime of the memory compared to the code with noninteracting stabilizers. We investigate how the fidelity, with which the toric code is realized, depends on the period length T of the pulse sequence and the magnitude of possible pulse errors. We derive an optimal period T_opt that maximizes the fidelity.

Hitachi dynamic memory RAM

Hitachi dynamic memory RAM

In this paper we describe a dynamic external memory data structure that supports range reporting queries in three dimensions in $O(\log_B^2 N + \frac{k}{B})$ I/O operations, where $k$ is the number of points in the answer and $B$ is the block size. This is the first dynamic data structure that answers three-dimensional range reporting queries in $\log_B^{O(1)} N + O(\frac{k}{B})$ I/Os.

The read channel of a Flash memory cell degrades after repetitive program and erase (P/E) operations. This degradation is often modeled as a function of the number of P/E cycles. In contrast, this paper models the degradation as a function of the cumulative effect of the charge written and erased from the cell. Based on this modeling approach, this paper dynamically allocates voltage using lower-voltage write thresholds at the beginning of the device lifetime and increasing the thresholds as needed to maintain the mutual information of the read channel in the face of degradation. The paper introduces the technique in an idealized setting and then removes ideal assumptions about channel knowledge and available voltage resolution to conclude with a practical scheme with performance close to that of the idealized setting.

In shared-memory concurrent programming, shared resources can be protected using synchronization mechanisms such as monitors or channels. The connection between these mechanisms and the resources they protect is, however, only given implicitly; this makes it difficult both for programmers to apply the mechanisms correctly and for compilers to check that resources are properly protected. This paper presents a mechanism to automatically check that shared memory is accessed properly, using a methodology called shared ownership. In contrast to traditional ownership, shared ownership offers more flexibility by permitting multiple owners of a resource. On the basis of this methodology, we define an abstract model of resource access that provides operations to manage data dependencies, as well as sharing and transfer of access privileges. The model is rigorously defined using a formal semantics, and shown to be free from data races. This property can be used to detect unsafe memory accesses when simulating the model together with the execution of a program. The expressiveness and efficiency of the approach is demonstrated on a variety of programs using common synchronization mechanisms.

In shared-memory concurrent programming, shared resources can be protected using synchronization mechanisms such as monitors or channels. The connection between these mechanisms and the resources they protect is, however, only given implicitly; this makes it difficult both for programmers to apply the mechanisms correctly and for compilers to check that resources are properly protected. This paper presents a mechanism to automatically check that shared memory is accessed properly, using a methodology called shared ownership. In contrast to traditional ownership, shared ownership offers more flexibility by permitting multiple owners of a resource. On the basis of this methodology, we define an abstract model of resource access that provides operations to manage data dependencies, as well as sharing and transfer of access privileges. The model is rigorously defined using a formal semantics, and shown to be free from data races. This property can be used to detect unsafe memory accesses when simulating the model together with the execution of a program. The expressiveness and efficiency of the approach is demonstrated on a variety of programs using common synchronization mechanisms.

From the bitsavers.org collection, a scanned-in computer-related document. vectorGraphic :: hardware :: 7200-2264-01-01 64K Dynamic Memory Board Oct80

From the bitsavers.org collection, a scanned-in computer-related document. vectorGraphic :: 7200-2264-01-01 64K Dynamic Memory Board Oct80

The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a novel design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect - giant circular birefringence (GCB) induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet - a mixture of all-optical Internet with quantum Internet.

Compared to quantum logic gates, quantum memory has received far less attention. Here, we explore the prognosis for a solid-state, scalable quantum dynamic random access memory (Q-DRAM), where the qubits are encoded by the spin orientations of single quantons in exchange-decoupled quantum dots. We address, in particular, various possibilities for implementing refresh cycles.

Tracklist: 1. Dynamic Memory Power 2. Dynamic Memory Power

Tracklist: 1. Dynamic Memory Power 2. Dynamic Memory Power

This is the preregistration of study 2 of an investigation into differences in memory between dynamic and static scenes in virtual reality (VR). Study 1 showed that dynamic scenes had higher encoding presence than static scenes. For retrieval, it also showed that recognition memory, subjective scene ratings from Rubin et al., 2019 (i.e., vividness, setting layout, event layout, and self-location), and objective scene recall (i.e, setting name and object location) were also higher for dynamic scenes than for static scenes. However, there was no difference between conditions when they had to recall two other objects in the scene. The aim of this study is to replicate the results from study 1, while also extending these findings. 1. Study 2 will track head movements to examine whether there is a difference between the dynamic and static conditions when experiencing the event during encoding. 2. We will remove the sound during encoding of the dynamic condition, to disentangle the sound and dynamism's role in our findings. 3. We will also change the encoding from being incidental to intentional encoding. This is to increase memory performance in the recognition task. Therefore, the overall goal of study 2, is replicate the results of study 1, that the dynamic condition have a better scene representation than the static condition. This would provide support for the dissociation between scene memory and object memory.