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Most lost of the digital design done today is synchronous that is a global synchronization signal is used to get the different parts to work in lockstep. It is simple and elegant and requires little circuit overhead. Yet as VLSI circuits increase in size and complexity. distributing global signals becomes more delicate, timing assumptions are harder to guarantee; at the system level, the global clock has to be slowed down to accommodate the slowest parts. It is interesting at this point, to consider asynchronous circuits where the time can be eliminated from the specification. A circuit is speed-independent when its correct operation is independent of delays operators circuit is delay-insensitive when its correct operation is independent of the delays in operators and wires except that the delays be finite [Sei80] [vdS85]. No global synchronization signal or knowledge about delays is used. As a subclass of asynchronous circuits delay-insensitive circuits are very interesting for formal design methods; we can reason about the correctness of such circuits independently of timing. Our research group has developed a synthesis method to compile a high level description of a circuit down to a gate level description [Mar86] [Mar90]. This compilation is largely technology- independent; only at the stage of sizing transistors for better performance do we have to look at the actual transistor network.