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The objective of this Phase-I study was to demonstrate the feasibility of a suite of industrial CAD tools for the design of high-performance, energy-efficient, asynchronous VLSI circuits based on the Caltech technology. Situs Logic's general strategy in the EDA-tools market is to develop and commercialize a complete suite of CAD tools for the design of asynchronous, QDI, VLSI systems including synthesis, analysis, simulation, verification, at the logical and physical levels. Situs has developed a business model for the commercialization of the CAD tools, and has designed the prototype of the tool suite based on this business model and the Caltech approach. The market for asynchronous tools will not be at first the mainstream market, but rather some 'early adopters' designing low-volume high-profit chips, for instance for defense or space applications. Inside the market segment of asynchronous VLSI tools, the competitive advantage pursued by Situs is differentiation rather than cost leadership, even though the Situs tools will be priced significantly below equivalent tools in the mainstream EDA market. The main technical activities and developments were directed towards the design of a prototype tool-site to test and demonstrate the feasibility of the approach. Although the design flow is not entirely automated yet-some steps still have to be preformed manually the results of the effort are very promising: The circuits synthesized with the prototype tool are easily competitive with the state of the art.