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This report describes the activities of the DEFACTO project, a Design Environment for Adaptive Computing Technology funded under the DARPA Adaptive Computing Systems and Just-In-Time-Hardware programs. The goal of DEFACTO is to derive system-level implementations of mappings to FPGA-based systems, from a high-level algorithmic description in standard C. We have demonstrated synthesis time reductions to 100-10000X with the automated design space exploration algorithm. The current reduction in design time, including human effort, has been approximately 40-60X for two case studies, SLD from Sandia ATR and Sobel edge detection. We have demonstrated end-to-end mapping on the Annapolis Wildstar board for both examples, with no minimal intervention, at DarpaTech on 31 July 2002.