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Dtic Ada393503%3a Georgia Tech Gt Viag%2c Vlsi Design Verification Document by Defense Technical Information Center
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1DTIC ADA393503: Georgia Tech GT-VIAG, VLSI Design Verification Document
By Defense Technical Information Center
There are eleven Georgia Tech VLSI designs in the AHAT Program. Each of these designs has been produced by Georgia Tech using the Genesil Silicon Compiler. Each design has passed the design verification process at Silicon Compiler Systems I Mentor Graphics and each has been fabricated in a bulk CMOS process (fabrication of certain chips was not complete when this document was released). Each of the Georgia Tech designs listed in Table 1 is being delivered to USASDC and to the Harris Corporation for conversion and fabrication in a rad-hard process. The program under which this work is done is AHAT (Advanced Hardened Avionics Technology). This document includes design information for the Georgia Tech instruction address generation chip, GT-VIAG.
“DTIC ADA393503: Georgia Tech GT-VIAG, VLSI Design Verification Document” Metadata:
- Title: ➤ DTIC ADA393503: Georgia Tech GT-VIAG, VLSI Design Verification Document
- Author: ➤ Defense Technical Information Center
- Language: English
“DTIC ADA393503: Georgia Tech GT-VIAG, VLSI Design Verification Document” Subjects and Themes:
- Subjects: ➤ DTIC Archive - Russ, Sam H - GEORGIA INST OF TECH ATLANTA COMPUTER ENGINEERING RESEARCH LAB - *VERY LARGE SCALE INTEGRATION - AVIONICS - CHIPS(ELECTRONICS) - COMPLEMENTARY METAL OXIDE SEMICONDUCTORS - RADIATION HARDENING
Edition Identifiers:
- Internet Archive ID: DTIC_ADA393503
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The book is available for download in "texts" format, the size of the file-s is: 129.35 Mbs, the file-s for this book were downloaded 60 times, the file-s went public at Thu May 03 2018.
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