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1DTIC ADA280909: Controlling Memory Access Concurrency In Efficient Fault-Tolerant Parallel Algorithms,
By Defense Technical Information Center
The CRCW PRAM under dynamic fail-stop (no restart) processor behavior is a fault-prone multiprocessor model for which it is possible to both guarantee reliability and preserve efficiency. To handle dynamic faults some redundancy is necessary in the form of many processors concurrently performing a common read or write task. In this paper we show how to significantly decrease this concurrency by bounding it in terms of the number of actual processor faults. We describe a low concurrency, efficient and fault-tolerant algorithm for the Write-All primitive: 'using less than or equal to N processors, write 1's into N locations'. This primitive can serve as the basis for efficient fault-tolerant simulations of algorithms written for fault-free PRAMs on fault-prone PRAMs. For any dynamic failure pattern F, our algorithm has total write concurrency less than or equal to /F/ and total read concurrency less than or equal to 7/F/log N, where /F/ is the number of processor faults (for example, there is no concurrency in a run without failures); note that, previous algorithms used Omega(N log N) concurrency even in the absence of faults. We also describe a technique for limiting the per step concurrency and present an optimal fault- tolerant EREW PRAM algorithm for Write-All, when all processor faults are initial.
“DTIC ADA280909: Controlling Memory Access Concurrency In Efficient Fault-Tolerant Parallel Algorithms,” Metadata:
- Title: ➤ DTIC ADA280909: Controlling Memory Access Concurrency In Efficient Fault-Tolerant Parallel Algorithms,
- Author: ➤ Defense Technical Information Center
- Language: English
“DTIC ADA280909: Controlling Memory Access Concurrency In Efficient Fault-Tolerant Parallel Algorithms,” Subjects and Themes:
- Subjects: ➤ DTIC Archive - Kanellakis, Paris C - BROWN UNIV PROVIDENCE RI DEPT OF COMPUTER SCIENCE - *ALGORITHMS - *MULTIPROCESSORS - *FAULT TOLERANCE - SIMULATION - MODELS - DYNAMICS - FAILURE - BEHAVIOR - FAULTS - REDUNDANCY - NUMBERS - EFFICIENCY - MEMORY DEVICES - RELIABILITY - GUARANTEES - PATTERNS
Edition Identifiers:
- Internet Archive ID: DTIC_ADA280909
Downloads Information:
The book is available for download in "texts" format, the size of the file-s is: 32.84 Mbs, the file-s for this book were downloaded 52 times, the file-s went public at Sun Mar 18 2018.
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