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This report presents descriptions and critiques of several low-level hardware fault insertion and instrumentation schemes for potential application in a digital flight control system (DFCS) simulator. Representing varying degrees of sophistication, these schemes are tailored to enhance test validity and productivity. Particular attention is therefore directed toward the capabilities offered by the various schemes, as well as their proper utilization. Factors such as fault detection coverage, latency time, and recovery from transients are stressed. Also, the role of the FIU is examined in detail. This tends to emphasize low-level fault injection, such as that on a chip pin level. Such testing should prove valuable despite the trend toward VLSI (Very Large-Scale Integration) circuits because correlation of present chip- versus-card fault observability may be useful in test case definition for VLSI implementations. Prepared under NASA Contract NAS2-11511, this study has been funded and technically supported by the Federal Aviation Administration.... Reliability, Fault monitoring, Digital flight control systems, Failure monitoring.