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The objective of this research is to provide an interconnect synthesis methodology which facilitates a modular design approach without compromising the global performance. The main tasks of this effort will be the development of the theory for optimal interconnect circuit synthesis from a high-level specification, with emphasis on testability and fault-tolerance asynchronous interface among concurrently computing hardware, and the application of this design methodology to physical implementations of parallel processing systems. Our major research effort has been directed toward the testability of asynchronous circuits. Testability has become a major design consideration in integrated circuit industry and the question that whether asynchronous circuits would simplify the testing tasks is to be answered. Asynchronous combinational circuits had been shown to be fully testable with single-stuck-at-faults (SSAFs) if precharged circuits were used for implementation; however, the testability of asynchronous control circuits (sequential circuits with environmental constraints) had not been addressed. Level-sensitive scan-path design can be used to aid testing in asynchronous sequential circuits, but scan-path design usually requires too long a testing day. We are most interested in incorporating testability directly into circuit synthesis. We considered the problem of testability for two areas of asynchronous design: speed-independent circuits and self-timed circuits.